ECEN 607(ESS ). Low DropOut Voltage Regulators. Analog and MixedSignal Center, Texas A&M University. Voltage. Battery (i.e. Liion). Regulated Voltage. Time. Power Management. Why do we need power management? Batteries discharge “almost” linearly with time.
Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.
Battery (i.e. Liion)
Regulated Voltage
Time
Power Management+
+
VREGULATED
Battery
Battery
Battery



VREGULATED
VREGULATED
CP
SR
LDO
LDO
CP
LDO
What are the conventional power converters?
Why do we need different Power Converters Types?
Can we combine them?
What is the purpose of combining several converters?
RC
RLOAD
VO
VBAT

RC
+
VC
Feedback
Control
RLOAD
VO
VBAT

Linear Regulator: PrinciplesThus in order to keep constant Vo, the value of the controlling resistor
RC yields:
How can we automatically pick the value of RC such that Vo= Vdesired, regvoltage?
b
a
b
a
b
VGS
VC = VGS
VC = VGS = VSG
RC1
RC2
RC1
RC2
a
b
a
b
MN
MP
VC
VC
How can we implement RC and the Feedback Control?ID
Can we implement RC as follows? For which applications?
NMOS Transistor
PMOS Transistor
ILOAD
Vdo = ILOADRC
VDO,p= VSD(SAT)
VDO,n= VSAT+Vgs
MN and MP are transistors operating in the Ohmic region. Discuss the option.
VO
R1
Error Amplifier
Error Amplifier
R1
VC,NMOS
VC,PMOS
R2
R2
VREF
VREF
How the feedback control could be implemented?OR
OR
Error Amplifier
VX
gm( Vx – ViN )
Ref
rop
PMOS Pass Transistor
AEA( VDIV  VREF)
AEA
VIN
R1
R1
Io
VDIV
VDIV
RL
Load (RL)
R2
R2
LDO AnalysisVIN = VBAT
Vo
Basic LDO Topology
Small Signal Representation
(1)
(2)
Where:
Thus Vo can be expressed as:
If
Vo yields:
T is the open loop gain. Furthermore for T >>1
Observe that Vin is attenuated by AEAand Vref is not.
The line regulation is a steadystate specification.It can be defined as:
For a practical case with nonidealities such as offset OpAmp voltage
and reference voltage error i.e.
; the line regulator becomes:
Observe that designers should also minimize:
and provide Vref to be independent of VBAT and temperature and process variations.
Note that Rc given in page 3 for a transistor can be expressed as:
In order to maintain the regulation the transistor must operate properly
NMOS case
Exercise: Repeat the above case for a PMOS case
GEA
∆VDIV
RL
RL
Vin
Vo+∆Vo
R2
VREF
Load/Line RegulationLet us assume the error amplifier is a transconductance amplifier of value GEAand α is the current gain of the pass transistor i.e.
Thus
Io
Furthermore:
Then, the load regulation can be expressed
as:
Or line regulation:
Io,max
Io,min
Io,min
t0
t1
t0
t1
t3
t4
Efficiency CalculationExample of efficiency: A 3.3V LDO with 3.7 V < Vin < 4.71V, 100mA < Io < 150mA
Io,q(maximum quiescent current) = 100 μA
The output current can be represented as a pulse for simulation purposes
OR
Im
RESR
Re
wL
CL
LDO ESR StabilityOne of the most challenging problems in designing LDO is the stability problems due to the closed loop and the parasitic components associated with the pass transistor and the error amplifier. In fact to compensate the loop stability a large external capacitor is often connected at the output. i.e.
Where CLis of the order of μF with a small equivalent series resistor (RESR).
voltage the input DC supply can attain and the regulated output
voltage.
regulated. The lower limit is dependent on the dropout voltage and
upper limit on the process capability.
of the regulated output voltage. The minimum current limit is mainly
dependent on the stability requirements and the maximum limit
dependent on Safe Operating Area (SOA) of pass FET and also
maintaining output voltage in regulation.
regulator is expected to accommodate without going unstable for a
given load current range.
the regulator guarantees. When output voltage is in this range, it is
said to be in regulation.
Error Amplifier
CGs
PND1
VREF
PD
C
Rds
Vout
PND2
B
CGD
R1
CL
RL
A
D
z
1EH
1EF
R2
RESR
VTest
Loop Breaking Point for Stability Analysis
Conventional LDO: ModelingClose Loop Schematic
Open Loop Transfer Function:
RPAR : Output impedance
RL : Load resistance
RDS : Drain to source impedance of the pass transistor
R1 &R2 : Feedback Resistors
Open Loop Block Diagram
Vdropout : Minimum voltage drop across the input and output terminalsof the LDO with shich the system is able to regulate.
VDSSATPass : Vdsat of the pass transistor
Note: The error amplifier is a twostage amplifier without miller compensation
Cgate
Error Amplifier AEATwo stage amplifier without miller compensation
Notes:
Transconductance
Dominant Pole / Compensation Zero
Nondominat Pole
due to Pass Transistor
Gate Capacitance
Error Amplifier
Nondominant Pole
Feedback
Factor
Matlab/Simulink MacromodelFormulas and Component Values
Fu ~ 2.7MHz
Phase boost due to Compensation Zero
PM ~ 90°
Simulation Results From SimulinkLoop Gain and Phase
Open Loop Gain and Phase Under Load Variation
Notes:
1Open Loop System
2 Load Variation (iload varies from 10mA to 50mA)
3 The load variation (iload) was simulated in Matlab using a “for loop”
VDD
VIN
VIN
VIN
Power Supply Rejection Existing SolutionsProposed Topology
G. A. RinconMora, V. Gupta, “A 5mA 0.6mA CMOS MillerCompensated LDO Regulator with 27dB WorstCase
PowerSupply Rejection Using 60pF of OnChip Capacitance ,” ISSCC, feb. 2007.
G. A. RinconMora, V. Gupta, “A 5mA 0.6mA CMOS MillerCompensated LDO Regulator with 27dB WorstCase
PowerSupply Rejection Using 60pF of OnChip Capacitance ,” ISSCC, feb. 2007.
Frequency Response
Open loop gain shows a low pass frequency response
AC signal is injected here
Loop Gain ~ 65dB
Fu ~ 10MHz
PM ~ 60°
AC signal is injected here
PSR versus Frequency
PSR curve shows a QuasiBand Pass frequency response
it is less than 40 dB up to 10KHz, 30 dB at 100 KHz
Robert J. Milliken, Jose SilvaMartínez, and Edgar SánchezSinencio “Full onchip CMOS lowdropout voltage regulator,”
IEEE Trans. on Circuits and Systems – I, pp 18791890, vol. 54, Issue 9, Sept. 2007.
Chaitanya K. Chava, and Jose SilvaMartinez, “A frequency compensation scheme for LDO voltage regulators,”
IEEE Trans. on Circuits and Systems – I, vol. 51, No.6, pp. 10411050, June 2004.
K. N. Leung, and P.K.T. Mok, “A capacitorfree CMOS lowdropout regulator with dampingfactorcontrol frequency compensation,” IEEE J. SolidState Circuits, vol.38, no.10, pp.16911702, Oct. 2003.
K. C. Kwok, P. K. T. Mok. “Polezero tracking frequency compensation for low dropout regulator,”
2002 IEEE International Symposium on Circuits and Systems, Vol. IV, pp. 735738,May 2002.
Yat Lei Lam, WingHung Ki, “A 0.9V 0.35µm Adaptively Biased CMOS LDO Regulator with Fast Transient Response,” 2008 IEEE International SolidState Circuit Conference, February 2008.
1. BandgapReference (Primary source of noise)
2. The resistor divider ( thermal noise = 4KTR )
3. Input stage of the error amplifier (thermal and flicker noise)
Reference: J. C. Teel, “Understanding noise in linear regulators” Analog Application Journal, 2Q 2005, www.ti.com/aaj
Vin
Vout
ILoad
RL
Vdropout
W/L
Design Error Amplifier
Cp
Rp
RA
CGate
RDS
Calculate non dominant poles: PND1, PND2
Adjust poles and zeros locations using CL and RESR
Check stability
Check transient, PSR, load regulation, line regulation, …
Since
Assuming
µPCox= 65µA/V2
the pass transistor size can be calculated by:
In order to minimize the gate capacitance, we use minimum length L = 0.6µm
The gate capacitance of the pass transistor is given by the following equation:
where
The values of CGS and CGD can be also obtained if we run a dc simulation and verify the operating point of the pass transistor. Using the last method, we found:
R1 and R2 are calculated using :
Assuming a reference voltage of 1.2V and choosing R1 = 240K, We found R2 = 420K .
Error Amplifier Design and Considerations
Error Amplifier schematic
The error amplifier is implemented using a two stage without miller compensation topology
in order to achieve a gain larger than 60dB and GBW =7MHz using 0.5µm CMOS technology
Error Amplifier Simulation Results
Phase Plot
Magnitude Plot
Note: This results were obtained using Cgate = 36.5pF as the load
Pole / Zero Locations
Dominant Pole Location
Second nondominant pole location
Zero location
First nondominant pole location
Notes:
1 RA was obtained from simulations. Basically, it is the output resistance of the error amplifier.
2PND2 is greater than 7.3MHz since the phase margin of the amplifier is around 51°. This is
good news since we want this pole to be located above the gain bandwidth product of the
overall system.
3 RESR equal 5 was chosen for stability reasons (see next slide).
Stability versus RESR
UGB versus RESR
Phase margin versus RESR
Note: RESR was swept from 0 to 10
System Simulation Results
Magnitude Plot (IL=50mA)
Phase Plot (IL=50mA)
Phase Margin = 55°
DC Gain = 74dB
UGB = 6.3MHz
Phase Plot (IL=100µA)
Magnitude Plot (IL=100µA)
Phase Margin = 90°
DC Gain = 75dB
UGB = 172KHz
System Simulation Results
VIN Step Plot
IL Step Plot
Load Regulation =
Line Regulation =
Notes:
1 VIN step from 3.4 to 3.5V
2 ILOAD step from 0 to 50mA
For low IL, for R1+R2 >> Ro_pass
Note that RL is significantly larger
Loop Gain:
For noload current
Note that GB will change as changes, this effects modify the polezero locations and the phase margin. i.e.,
Current Efficient LDODue to current mirror when load current exist, then we have
make
The zero is located at:
Another pole is located at the output of the AEA,
G. A. RinconMora, P. E. Allen, “A lowvoltage, low quiescent current, low dropout regulator,”
IEEE J. SolidState Circuits, vol.33, no.1, pp.3644, Jan. 1998.
Avo
p1
p2
p3
z
To determine the stability one can consider the open loop gain defined as:
where
Stability imposes the following conditions:
where
Where o is defined as:
Or
Phase Margin:
;
is the arbitrary phase margin
In order to determine an approximated relation between p3 and GB several assumptions are required.
Avo >> 1, Then tan1(Avo) 90°
Thus one can write
p3 100GBW
PM 45°
p3 GBW
Open Loop Gain and Phase For Different p3 Locations
Notes:
1Open Loop System
2 The location of p3 was varied
3 The variation (p3) was simulated in Matlab using a “for loop”
Courtesy of Tuli Dake from TI
[1] G. A. RinconMora, V. Gupta, “A 5mA 0.6mA CMOS millercompensated LDO regulator with 27dB worstcase powersupply rejection using 60pF of onchip capacitance ,” ISSCC, Feb. 2007.
[2] L.G. Shen et al., “Design of lowvoltage lowdropout regulator with wideband highPSR characteristic,” International Conference on SolidState and Integrated Circuit Technology, ICSICT, Oct. 2006.
[3] R. J. Milliken, J. SilvaMartínez, and E. SánchezSinencio, “Full onchip CMOS lowdropout voltage regulator,” IEEE Trans. on Circuits and Systems – I, pp 18791890, vol. 54, Issue 9, Sept. 2007.
[4] C. K. Chava, and J. SilvaMartinez, “A frequency compensation scheme for LDO voltage regulators,” IEEE Trans. on Circuits and Systems – I, vol. 51, No.6, pp. 10411050, June 2004.
[5] K. N. Leung, and P.K.T. Mok, “A capacitorfree CMOS lowdropout regulator with dampingfactorcontrol frequency compensation,” IEEE J. SolidState Circuits, vol.38, no.10, pp.16911702, Oct. 2003.
[6] K. C. Kwok, P. K. T. Mok. “Polezero tracking frequency compensation for low dropout regulator,” 2002 IEEE International Symposium on Circuits and Systems, Vol. IV, pp. 735738, May 2002.
[7] J. C. Teel, “Understanding noise in linear regulators” Analog Application Journal, 2Q 2005, www.ti.com/aaj
[8] K. N. Leung, P. K. T. Mok, and W. H. Ki, "A novel frequency compensation technique for lowvoltage lowdropout regulator," IEEE International Symposium on Circuits and Systems, vol. 5, May 1999.
[9] G. A. RinconMora and P. A. Allen, "A lowvoltage, low quiescent current, low dropout regulator," IEEE J. SolidState Circuits, vol.33, no.1, pp.3644, Jan. 1998.