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## Low-voltage techniques

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**Low-voltage techniques**Mohammad Sharifkhani**Reading**• Text Book I, Chapter 4 • Text Book II, Section 11.7**Power, Energy, Speed**• Speed • Energy Battery lifetime • Instantaneous power Package, cooling If leakage is ignored, P x Tpd is equal to E; independent of Vth and Speed: work at the slowest speed; lowest VDD to minimize E (and P).**Power, Energy, Speed**• Both Energy and Speed are important: • Energy x Delay is the right index (?) • To minimize power • Lower VDD (quadratic dependence, +both leakage and dynamic power) • Reduce C • Lower pt • Lower VDD Delay 4 possibilities • Dual Vth (low Vth only for critical path) • Multiple VDD (low VDD for non critical path) • Parallel, pipeline arch. • Lower Vth to recover the speed**Architecture Trade-off for Fixed-rate ProcessingReference**Datapath**Multiple supply issues**Still on! DC current**Optimum V2/V1 is around 0.7V**Hamada, CICC’01**Multiple supply voltages**• Two supply voltages per block are optimal • Optimal ratio between the supply voltages is 0.7 • Level conversion is performed on the voltage boundary, using a level-converting flip-flop (LCFF) • An option is to use an asynchronous (combinatorial) level converter • More sensitive to coupling and supply noise**VDD temporal variation**• Design for Dynamically Varying VDD • • Ring oscillator. • • static logic • • Dynamic logic (& tri-state busses). • • Sense amp (& memory cell). • Max. allowed |dVDD/dt| → Min. CDD = 100nF (0.6μm) • Circuits continue to properly operate as VDD changes VDD t