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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. Layout for ASIC netlist Results of Phase 4 Michael Rethfeldt. ASIC n etlist. set target_library [ concat $CORESVTtyp10V $COREHVTtyp10V $CORELVTtyp10V] set_operating_conditions nom_1.00V_25C

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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

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  1. Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Layout for ASIC netlist Resultsof Phase 4 Michael Rethfeldt

  2. ASIC netlist set target_library [concat $CORESVTtyp10V $COREHVTtyp10V $CORELVTtyp10V] set_operating_conditions nom_1.00V_25C setfrequency110 (was 100) set_max_leakage_power 100 nW ungroup -all -flatten -simple_names compile_ultra -area_high_effort_script

  3. ASIC layout – positive effects • Core utilization • - freq. bestaround 90 % • below longwirestocoresides, slower • above limited routingpossibilities, slower • Core aspectratio • - IO padsleft & right  H > W (0.9:1, 1.5:1, 2:1, 3:1, 4:1, 5:1) • Antennafixing • - turned off in nano-route  slightspeedincrease

  4. ASIC layout – negative effects • Limited metalusage • limited tolayer 4 (5 usedbefore) • speeddecrease • Post route optimizations • timingonly • leakageonly • leakage & timing •  alwayshighleakageincrease • Gate libraries • useonlyhighVtinsteadofmixedVt • -2nW leakage, speeddecrease  worsemetric • Power stripes •  speeddecrease (place & route limitation)

  5. ASIC layout – misc. • Power ring dimensions • tried 2µm, 5µm, 10µm width •  noeffects on speed / leakageforused design

  6. Final ASIC layout withpads leakage > 12 mW !!

  7. Metric ASIC netlist phase 3

  8. Metric ASIC layout phase 4

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