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## CMOS VLSI Design Lecture 1 3 : Design for Low Power

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Outline

- Why low power design?
- Power and Energy
- Dynamic Power
- Static Power
- Low Power Design

13: Design for Low Power

Needs for Low Power VLSI Chips

- Power dissipation was neglected due to
- Low device density
- Low operating frequency
- Now it is important issue due to
- High device density
- High operating frequency
- Proliferation of portable consumer electronics
- Concerns on Environments and energy sources

13: Design for Low Power

Moore’s Law

- In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.
- He made a prediction that semiconductor technology will double its effectiveness every 18 months

13: Design for Low Power

Evolution in Complexity

13: Design for Low Power

Transistor Counts

1 Billion Transistors

K

1,000,000

100,000

Pentium® III

10,000

Pentium® II

Pentium® Pro

1,000

Pentium®

i486

i386

100

80286

8086

10

Source: Intel

1

1975

1980

1985

1990

1995

2000

2005

2010

Projected

13: Design for Low Power

Courtesy, Intel

Moore’s law in Microprocessors

1000

2X growth in 1.96 years!

100

10

P6

Pentium® proc

Transistors (MT)

486

1

386

0.1

286

8086

8085

0.01

8080

8008

4004

0.001

1970

1980

1990

2000

2010

Year

Transistors on Lead Microprocessors double every 2 years

13: Design for Low Power

Courtesy, Intel

Die Size Growth

100

P6

Pentium ® proc

486

Die size (mm)

10

386

286

8080

8086

~7% growth per year

8085

8008

~2X growth in 10 years

4004

1

1970

1980

1990

2000

2010

Year

Die size grows by 14% to satisfy Moore’s Law

13: Design for Low Power

Courtesy, Intel

Frequency

10000

Doubles every2 years

1000

P6

100

Pentium ® proc

Frequency (Mhz)

486

386

10

8085

286

8086

8080

1

8008

4004

0.1

1970

1980

1990

2000

2010

Year

Lead Microprocessors frequency doubles every 2 years

13: Design for Low Power

Courtesy, Intel

Power Dissipation

100

P6

Pentium ® proc

10

486

286

8086

Power (Watts)

386

8085

1

8080

8008

4004

0.1

1971

1974

1978

1985

1992

2000

Year

Lead Microprocessors power continues to increase

13: Design for Low Power

Courtesy, Intel

Power will be a major problem

100000

18KW

5KW

10000

1.5KW

500W

1000

Pentium® proc

Power (Watts)

100

286

486

8086

10

386

8085

8080

8008

1

4004

0.1

1971

1974

1978

1985

1992

2000

2004

2008

Year

Power delivery and dissipation will be prohibitive

13: Design for Low Power

Courtesy, Intel

Nozzle

Nuclear

Reactor

Hot Plate

Power densitySun Surface

10000

1000

Power Density (W/cm2)

100

8086

10

4004

P6

8008

Pentium® proc

8085

386

286

486

8080

1

1970

1980

1990

2000

2010

Year

Power density too high to keep junctions at low temp

13: Design for Low Power

Courtesy, Intel

Signal RF

Power

RF

Power

Management

1996 1997 1998 1999 2000

Units48M 86M 162M 260M 435M

Analog

Baseband

Digital Baseband

(DSP + MCU)

Not Only MicroprocessorsCellPhone

Digital Cellular Market

(Phones Shipped)

(data from Texas Instruments)

13: Design for Low Power

Battery

- Portable consumer electronics powered by battery
- Battery is heavy and big
- Energy density barely doubles in several years
- Safety concern: the energy density is approaching

that of explosive chemicals.

The battery technology alone will not solve the low power problem

13: Design for Low Power

Reliability and Cooling Costs

- High power dissipation high temperature malfunction
- High performance microprocessors: ~50 Watts (a hand-held soldering iron)
- Packaging cost and cooling cost: fans
- Power supply rails: high transient current (e.g. 3A).

13: Design for Low Power

Environmental Concerns

- Office automation equipment
- 5% of total US commercial energy in 1993
- 10% of total US commercial energy in 2000
- Electricity generation air pollution and consumption of energy sources

13: Design for Low Power

Power and Energy

- Power is drawn from a voltage source attached to the VDD pin(s) of a chip.
- Instantaneous Power:
- Energy:
- Average Power:

13: Design for Low Power

Dynamic Power

- Dynamic power is required to charge and discharge load capacitances when transistors switch.
- One cycle involves a rising and falling output.
- On rising output, charge Q = CVDD is required
- On falling output, charge is dumped to GND
- This repeats Tfsw times

over an interval of T

13: Design for Low Power

Dynamic Power Cont.

13: Design for Low Power

Dynamic Power Cont.

13: Design for Low Power

Activity Factor

- Suppose the system clock frequency = f
- Let fsw = af, where a = activity factor
- If the signal is a clock, a = 1
- If the signal switches once per cycle, a = ½
- Dynamic gates:
- Switch either 0 or 2 times per cycle, a = ½
- Static gates:
- Depends on design, but typically a = 0.1
- Dynamic power:

13: Design for Low Power

Short Circuit Current

- When transistors switch, both nMOS and pMOS networks may be momentarily ON at once
- Leads to a blip of “short circuit” current.
- < 10% of dynamic power if rise/fall times are comparable for input and output

13: Design for Low Power

Example

- 200 Mtransistor chip
- 20M logic transistors
- Average width: 12 l
- 180M memory transistors
- Average width: 4 l
- 1.2 V 100 nm process
- Cg = 2 fF/mm

13: Design for Low Power

Dynamic Example

- Static CMOS logic gates: activity factor = 0.1
- Memory arrays: activity factor = 0.05 (many banks!)
- Estimate dynamic power consumption per MHz. Neglect wire capacitance and short-circuit current.

13: Design for Low Power

Dynamic Example

- Static CMOS logic gates: activity factor = 0.1
- Memory arrays: activity factor = 0.05 (many banks!)
- Estimate dynamic power consumption per MHz. Neglect wire capacitance.

13: Design for Low Power

Static Power

- Static power is consumed even when chip is quiescent.
- Ratioed circuits burn power in fight between ON transistors
- Leakage draws power from nominally OFF devices

13: Design for Low Power

Leakage Example

- The process has two threshold voltages and two oxide thicknesses.
- Subthreshold leakage:
- 20 nA/mm for low Vt
- 0.02 nA/mm for high Vt
- Gate leakage:
- 3 nA/mm for thin oxide
- 0.002 nA/mm for thick oxide
- Memories use low-leakage transistors everywhere
- Gates use low-leakage transistors on 80% of logic

13: Design for Low Power

Leakage Example Cont.

- Estimate static power:
- High leakage:
- Low leakage:
- If no low leakage devices, Pstatic = 749 mW (!)

13: Design for Low Power

Low Power Design

- Reduce dynamic power
- a: clock gating, sleep mode
- C:
- VDD:
- f:
- Reduce static power

13: Design for Low Power

Low Power Design

- Reduce dynamic power
- a: clock gating, sleep mode
- C: small transistors (esp. on clock), short wires
- VDD:
- f:
- Reduce static power

13: Design for Low Power

Low Power Design

- Reduce dynamic power
- a: clock gating, sleep mode
- C: small transistors (esp. on clock), short wires
- VDD: lowest suitable voltage
- f:
- Reduce static power

13: Design for Low Power

Low Power Design

- Reduce dynamic power
- a: clock gating, sleep mode
- C: small transistors (esp. on clock), short wires
- VDD: lowest suitable voltage
- f: lowest suitable frequency
- Reduce static power

13: Design for Low Power

Low Power Design

- Reduce dynamic power
- a: clock gating, sleep mode
- C: small transistors (esp. on clock), short wires
- VDD: lowest suitable voltage
- f: lowest suitable frequency
- Reduce static power
- Selectively use ratioed circuits
- Selectively use low Vt devices
- Leakage reduction:

stacked devices, body bias, low temperature

13: Design for Low Power

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