Propagation Delay Stability in Logic Devices. Richard B. Katz NASA Office of Logic Design 2004 MAPLD International Conference September 8-10, 2004 Washington, D.C. Abstract.
Richard B. Katz
NASA Office of Logic Design
2004 MAPLD International Conference
September 8-10, 2004
This paper will present data on propagation delays in logic devices, examining their distributions, the effects of life on propagation delay, and the characteristics of the changes in delays. Factory life test/qualification data will be presented along with recently taken in the evaluation of damage to programmed antifuses.
Analysis of the data will be used to examine existing design rules, but for min/max analysis as well as those pertaining to the relative changes in delays.
Binning Delay Delta Data Summary (ns)
Tested at VDD = 4.5V; T = 125 ºC
RTSX32S tPD sensitive to total ionizing dose in a Co-60 irradiation chamber. Design changes in the RTSX72S reduced the sensitivity to acceptable levels. These design changes were incorporated into the next revision of the RT54SX32S.
The following chart shows aggregate data from multiple lots of RT54SX72S FPGAs, totaling 1,040 individual devices. The speed data, with a mean delay of 73.8 ns, is measurements of the binning circuit, representative of logic paths, and is used to determine the device speed grade. Note that the delays over life do not necessarily "track," as there are both differences in the changes of delay as well as some differences in the sign of a delay change.
I hate ring oscillators; use a clock..
Intrinsic distribution is tightly grouped. Outliers are devices with damaged programmed antifuses.
All delays are in ns.
Damaged programmed antifuses show signs of instability over the course of the test.
Note S/N 34319 first decreases in speed and then returns close to its initial value.
Intrinsic population is stable over the course of the test. Outliers are devices with damaged programmed antifuses with delta delays ranging from 10’s of ns to hundreds of ns. Other data shows delays from damaged devices may exceed 1 µs. Mean delay is ~ 930 µs.
Frequency measurement at startup. Ring oscillator period increases for a considerable period of time before stabilizing, likely a result of self-heating, as digital CMOS slows with
increased temperature. One of the two “practice parts” shows a discontinuity.
Frequency measurement of three devices with damaged programmed antifuses. Note the discontinuity, showing instability of the damaged element. Additional test data confirmed the instability of damaged programmed antifuses in a different S/N device.
Intrinsic distribution is tightly grouped. 100 devices, ~20 the number used in the SX32S test.
All delays are in ns.
Intrinsic population is stable over the course of the test. Mean delay is ~ 1,125 ns; deltas, even with measurement errors, are less then 1%.
The testing will consist of exposing devices to a dynamic operating environment with multiple stressors:
Testing will proceed in a series of stress steps, the duration of each step will be 480 hours, with 240 hours at +125 °C and 240 hours at -55 °C.
Fill in final values