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PCB DESIGN Dr. P. C. Pandey EE Dept, IIT Bombay Revised Aug’07. Topics General Considerations in Layout Design Layout Design for Analog Circuits Layout Design for Digital Circuits Artwork Considerations References

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Pcb design dr p c pandey ee dept iit bombay revised aug 07

PCB DESIGN

Dr. P. C. Pandey

EE Dept, IIT Bombay

Revised Aug’07


Pcb design dr p c pandey ee dept iit bombay revised aug 07

  • Topics

    • General Considerations in Layout Design

    • Layout Design for Analog Circuits

    • Layout Design for Digital Circuits

    • Artwork Considerations

    • References

    • W.C. Bosshart, Printed Circuit Boards: Design and Technology, TMH, 1992

    • C.F. Coombs : Printed Circuits Handbook , McGraw-Hill, 2001

    • R.S. Khandpur : Printed Circuit Boards : Design, Fabrication, and Assembly, McGraw-Hill, 2005.


Pcb design dr p c pandey ee dept iit bombay revised aug 07

GENERAL CONSIDERATIONS IN LAYOUT DESIGNMain issues• Component interconnections • Effects of parasitics• Physical accessibility of components • Power dissipationSubtopics 1.1 Parasitic effects1.2 Supply conductors1.3 Component placement


Pcb design dr p c pandey ee dept iit bombay revised aug 07

1.1 Parasitic EffectsR & L of conductor tracksC between conductor tracksResistanceResistance of 35 μm thickness, 1 mm wide conductor = 5 mΩ/cmChange in Cu resistance with temperature = 0.4% / °CCurrent carrying capacity of 35 μm thickness Cu conductor (for 10 °C temperature rise): Width (mm) 1 4 10 Ic (A) 2 4 11


Pcb design dr p c pandey ee dept iit bombay revised aug 07

Capacitance

• Tracks opposite each other

- Run supply lines above each other

- Don’t let signal line tracks overlap for any significant distance

• Tracks next to each other

- Increase the spacing between critical conductors

- Run ground between signal lines

Inductance

To be considered in

•High frequency analog circuits

• Fast switching logic circuits


Pcb design dr p c pandey ee dept iit bombay revised aug 07

1.2 Supply ConductorsUnstable supply & ground due to• Resistive voltage drop• Voltage drop caused by track L and high freq. current• Current spikes during logic switching  local rise in ground potential & fall in Vcc potential  possibility of false logic triggering.Solutions•Conductor widths : W (ground) > W (supply) > W(signal)• Ground plane• Track configuration for distributed C between Vcc & ground• Analog & digital ground (&supply) connected at the most stable point


Pcb design dr p c pandey ee dept iit bombay revised aug 07

1.3 Component Placement•Minimize critical conductor lengths & overall conductor length • Component grouping according to connectivity • Same direction & orientation for similar components • Space around heat sinks •Packing density• Uniform • Accessibility for • adjustments • component replacement • test points • Separation of heat sensitive and heat producing components •Mechanical fixing of heavy components


Pcb design dr p c pandey ee dept iit bombay revised aug 07

2. LAYOUT DESIGN FOR ANALOG CIRCUITS• Supply and ground conductors • Signal conductors for reducing the inductive and capacitive coupling • Special considerations for • Power output stage circuits • High gain direct coupled circuits • HF oscillator /amplifier • Low level signal circuits


Pcb design dr p c pandey ee dept iit bombay revised aug 07

2.1 Ground & Supply Lines• Separate GND (& Vcc) lines for analog & digital circuits• Independent ground for reference voltage circuits• Connect different ground conductors at most stable

reference point

• Supply lines with sufficient

width and high capacitive

coupling to GND

(use decoupling capacitors)

• Supply line should first

connect to high current drain

ckt blocks

• Supply line independent for voltage references


Pcb design dr p c pandey ee dept iit bombay revised aug 07

2.2 HF Oscillator / Amplifier

• Decoupling capacitor between Vcc & GND  Capacitive load on o/p

• Reduce capacitive coupling between output & input lines

• Vcc decoupling for large BW ckts. (even for LF operation)

• Separation between signal & GND to reduce capacitive loading


Pcb design dr p c pandey ee dept iit bombay revised aug 07

2.3 Circuits with High Power O/P StageResistance due to track length & solder joints  modulation of Vcc & GND and low freq. oscillations • Large decoupling capacitors • Separate Vcc & GND for power & pre- amp stages


Pcb design dr p c pandey ee dept iit bombay revised aug 07

2.4 High Gain DC AmplifierSolder joints  thermocouple jnTemp gradients  diff. noisy voltages • Temp.gradients to be avoided • Enclosure for stopping free movement of surrounding air


Pcb design dr p c pandey ee dept iit bombay revised aug 07

2.5 Low Level Signal Circuits

A) High impedance circuits - Capacitive coupling

B) Low impedance circuits - Inductive coupling


Pcb design dr p c pandey ee dept iit bombay revised aug 07

High -Z circuitsIf R » 1∕ jw(Cxy+Cy)then coupled Vy = Va × [Cxy/(Cy+Cxy)]• Increase separation between low level high Z line and high level line(decrease Cxy)• Put a ground line between the two (guard line)Example:Guard for signal leakage from FET output to input


Pcb design dr p c pandey ee dept iit bombay revised aug 07

Low – Z Circuits• Voltage induced in ground loops due to external magnetic fields • Current caused in the low- Z circuit loop due to strong AC currents in nearby circuits Vm= - (d/dt) B dA• Avoid ground loops • Keep high current ac lines away from low level,low Z circuit loops • Keep circuit loop areas small


Pcb design dr p c pandey ee dept iit bombay revised aug 07

3. LAYOUT DESIGN FOR DIGITAL CIRCUITS

Main problems

• Ground & supply line noise

• Cross-talk between neighboring signal lines

• Reflections : signal delays, double pulsing


Pcb design dr p c pandey ee dept iit bombay revised aug 07

3.1 Ground & Supply Line Noise

Noise generated due to current spikes during logic level switching,

drawn from Vcc and returned to ground

• Internal spike: charging & discharging of transistor junction capacitances in IC ( 20 mA, 5ns in TTL)

• External spike: charging & discharging of output load capacitance

Ground potential increases, Vcc decreases: improper logic triggering.

Problem more severe for synchronous circuits.

Severity of problem (increasing): CMOS, ECL, TTL.


Pcb design dr p c pandey ee dept iit bombay revised aug 07

Solution for ground & supply noise

• Decoupling C between Vcc & ground for every 2 to 3 IC’s :

ceramic, low L cap. of 10 nf for TTL & 0.5 nF for ECL & CMOS

•Stabilizes Vcc-GND (helps against internal spikes

• Not much help for external spikes

• Low wave impedance between supply lines (20 ohms):

5 to 10 mm wide lines opposite each other as power tracks

•Ground plane : large Cu area for ground

to stabilize it against external spikes

• Closely knit grid of ground conductors

(will form ground loops, not to be used for analog circuits)

• Twist Vcc & GND line between PCBs


Pcb design dr p c pandey ee dept iit bombay revised aug 07

3.2 Cross-talk

• Occurs due to parallel running signal lines

(ECL: 10cm,TTL: 20 cm, CMOS: 50 cm)

• Problem more severe for logic signals flowing in opposite directions

Solutions

• Reduce long parallel paths

• Increase separation

betw. signal lines

• Decrease impedance

betw. signal & ground lines

• Run a ground track

between signal lines


Pcb design dr p c pandey ee dept iit bombay revised aug 07

3.3 Reflections

Caused by mismatch between the logic output impedance

& the wave impedance of signal tracks.

• Signal delay (low wave imp.) • Double pulses (high wave imp.)

TTL (Z: 100 - 150 )

0.5 mm signal line with GND plane, 1 mm without GND plane.

Signal lines between PCBs twisted with GND lines.

ECL (Z: 50 )

1 - 3 mm signal line with GND plane, or nearby gnd conductor.

CMOS (Z: 150 – 300 )

0.5 mm signal line without GND plane. Gnd not close to signal lines.


Pcb design dr p c pandey ee dept iit bombay revised aug 07

CMOS

Logic Family:

TTL

ECL

Signal–GND Zw ()

100 - 150

50 - 100

150 - 300

Signal line width (mm)

0.5 with gnd

1, no gnd

1 - 3 with gnd

0.5, no gnd

Vcc -GND Zw ()

< 5

< 10

< 20

Vcc line (mm)

5

2 to 3

2

GND line (mm)

Very broad

(plane /grid)

Broad

(plane/grid)

5

Summary of Layout Design Considerations

(for 1.6 mm thickness, double sided boards)


Pcb design dr p c pandey ee dept iit bombay revised aug 07

4. ARTWORK RULES

Conductor orientation

• Orientation for shortest interconnection length.

• Conductor tracks on opposite sides in x-direction & y-direction to minimize via holes.

• 45° or 30° / 60° orientation for turns.

Conductor Routing

• Begin and end at solder pads, join conductors for reducing interconnection length.

• Avoid interconnections with internal angle <60°.

• Distribute spacing between conductors .


Pcb design dr p c pandey ee dept iit bombay revised aug 07

Conductor 

routing

examples


Pcb design dr p c pandey ee dept iit bombay revised aug 07

  • Solder Pads

  • Hole dia

    • •Reduce the number of different sizes.

    • • 0.2 - 0.5 mm clearance for lead dia.

  • Solder pad

    • •Annular ring width

    • ≥ 0.5 mm with PTH

    • ≈ 3 × hole dia without PTH

      • Uniformity of ring around the hole.

      • Conductor width d > w > d/3.