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CPE/EE 428, CPE 528 Testing Combinational Logic (3)

CPE/EE 428, CPE 528 Testing Combinational Logic (3). Department of Electrical and Computer Engineering University of Alabama in Huntsville. FF’s. d. Q. Combinational logic. d. Q. …. d. Q. load enable/shift. scan chain shiftin/out. Testing Digital Systems.

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CPE/EE 428, CPE 528 Testing Combinational Logic (3)

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  1. CPE/EE 428, CPE 528 Testing Combinational Logic (3) Department of Electrical and Computer Engineering University of Alabama in Huntsville

  2. FF’s d Q Combinational logic d Q … d Q load enable/shift scan chain shiftin/out Testing Digital Systems • Combinational vs Sequential Systems • We shall cover combinational first • Sequential circuits can be tested using combinational test generation and scan chains • The state FF’s are connected in a shift register. Any value can be shifted in (setting an arbitrary state), the next state loaded, and then shifted out. Thus tests can be directly applied to the combinational logic. VLSI Design II: VHDL

  3. x Z(x) N Testing Digital Systems: Detection • Detecting a fault • A test vector t is an assignment of input values. It detects a fault f iff Z(t)  Z f (t) • The set of all tests {T} that detects f is found by Z(x)  Z f (x) = 1 A good circuit N produces function Z(x) A circuit with fault f produces a different function Z f (x) x Z f (x) N f VLSI Design II: VHDL

  4. Testing Digital Systems: Detection • Assume x4 s-a-0 (stuck-at 0, sa0) x2 x3 x1 Good Circuit Z x4 x2 x3 x1 Faulty Circuit Zf VLSI Design II: VHDL

  5. Testing Digital Systems: Detection test for x4 s-a-0 • This says that any input vector with x1 = 0 and x4 = 1 is a test vector for x4 s-a-0. x2 and x3 are don’t-cares. x2 (a+b)  a = ? = (a+b) a’ + (a+b)’ a = aa’ + a’b + (a’ • b’) a = a’b = ((x2+x3)x1)’ • x1’x4 = (cx1)’ • x1’x4 = (c’ + x1’) • x1’x4 = c’x1’x4 + x1’x4 = x1’x4 x3 x1 Z x4 Z(x)  Z f (x) = 1 Z = (x2 + x3) x1 + x1’x4 Z f = (x2 + x3) x1  —> x1’x4 = 1 VLSI Design II: VHDL

  6. Testing Digital Systems: Detection • The combined good/bad circuit can be drawn • values shown are for v/vf • that is, values in the good circuit / values in the faulty circuit • v/vf shows a discrepancy between good/faulty circuit values x2 x3 0 0 test for x4 s-a-0 x1 0 1/0 Z 1 1 x4 1/0 1/0 s-a-0 VLSI Design II: VHDL

  7. Fault Activation and Propagation • Two basic concepts in fault detection illustrated • A test must activate the fault by creating different v/vf values at the fault site • thus x4 is assigned to be 1. If it really is stuck at zero, we know there will be a change in circuit values. • A test must propagate the error to a primary output • other circuit values must be selected to allow the good/faulty value to be seen at an output. x2 x3 0 0 x1 0 1/0 Z test for x4 s-a-0 1 1 x4 1/0 1/0 s-a-0 VLSI Design II: VHDL

  8. Path Sensitization • Path sensitization • A line whose value (with the test t) changes in the presence of fault f is said to be sensitized to fault f by test t • these lines are indicated by having different v/vf values • A path composed of sensitized lines is a sensitized path x2 x3 0 0 x1 0 1/0 Z test for x4 s-a-0 1 1 x4 1/0 1/0 Sensitized path s-a-0 VLSI Design II: VHDL

  9. Another example • Test x1 s-a-0 x2 x3 x1 Z x4 s-a-0 VLSI Design II: VHDL

  10. c i AND 0 0 OR 1 0 NAND 0 1 NOR 1 1 Controlling and Inverting Values • Aside • Primitive logic gates (AND, OR, NAND, NOR) can be characterized by two parameters • controlling value — c • inversion — i • Controlling value • the value when on any one input will determine the gate’s output regardless of the other inputs • (e.g. 0 on any AND gate input) • If one input has the controlling value, the gate’s output will be • c  i, where c and i come from the following table VLSI Design II: VHDL

  11. c i AND 0 0 OR 1 0 NAND 0 1 NOR 1 1 Controlling and Inverting Values • Along the sensitized path • any input sensitized to the fault will have a value, call it d • all other inputs will have c’ (complement of controlling value) • a non-controlling, or enabling, value • the output will have value d  i d d’ 1 d d d could be 1/0 or 0/1 VLSI Design II: VHDL

  12. c i AND 0 0 OR 1 0 NAND 0 1 NOR 1 1 Controlling and Inverting Values x2 x3 0 0 x1 0 1/0 Z 1 1 x4 1/0 1/0 s-a-0 Which are controlling, which are enabling? VLSI Design II: VHDL

  13. Testing Digital Circuits: Redundancy • Fault f is detectable if there exists a test t that detects it i.e. Z(t)  Z f (t) • However, f is undetectable if Z(x) = Z f (x) for all x • Cool! There are some circuits where even if there is a fault in certain places, they still work! • A circuit that contains an undetectable fault is a redundant circuit. • The fault site obviously has no effect on the circuit function • The circuit can be simplified — you can remove something! VLSI Design II: VHDL

  14. Testing Digital Circuits: Redundancy • Example: • F = ab + bc + a’c • Is the fault Y s-a-0 detectable? • Activate and propagate Y s-a-0 X a b Y F c Z VLSI Design II: VHDL

  15. ab X a 00 01 11 10 c b 0 1 1 Y c 1 1 1 Z term bc is redundant Redundancy • Y s-a-0 is undetectable • F = ab + bc + a’c = ab + a’c • The term bc is a redundant cover in the Kmap • it’s not an essential implicant of the function — the other two are • Change to circuit • Gate Y can be removed from the circuit without affecting the logic function. • Or you can keep it and have some fault tolerance VLSI Design II: VHDL

  16. Redundancy — Pro and Con • Pro and Con • The fault is undetectable. • This can be good! The circuit still works even if there are certain faults in it. • Are others undetectable too? — or harder to detect • The redundant circuit requires extra hardware — extra area on the IC VLSI Design II: VHDL

  17. ab x 00 01 11 10 c 0 1 1 1 1 1 z Redundancy — Pro and Con • The circuit is hazard free on transition 111 —> 011 • Hazard — the value of the function takes on an intermediate value different from the final value • With a non-redundant circuit, there is a chance of a 1 - 0 - 1 hazard • With the redundant circuit, if the inputs change from 111 —> 011, the output will not go to zero. Are there other such transitions? X a b Y c Z VLSI Design II: VHDL

  18. Undetectable fault Simplification Rule AND (NAND) input s-a-1 Remove input AND (NAND) input s-a-0 Remove gate, replace by 0 (1) OR (NOR) input s-a-0 Remove input OR (NOR) input s-a-1 Remove gate, replace by 1 (0) Testing Digital Circuits: Redundancy • Removing redundant covers • Other redundancies • Triple modular redundancy — a method for achieving fault tolerance. • faults are correct by additional logic • many faults would be untestable — they’d be automatically corrected • … and logic synthesis would optimize the redundancy away! • Need a test mode to disable correction VLSI Design II: VHDL

  19. Testing: is it so simple? • Test engineers = Sherlock Holmes of the industry • Methods for automatically generating tests were necessary • Collectively known as ATPG =>Automatic Test Pattern Generation VLSI Design II: VHDL

  20. D (Dbar) = 0/1 - represents a logic 0 in the good circuit and a logic 1 in the bad circuit D-Calculus D (Detect) = 1/0 - represents a logic 1 in the good circuit and a logic 0 in the bad circuit Five-valued logic: 0, 1, D, Dbar, X (don’t care) VLSI Design II: VHDL

  21. D-Calculus Truth tables for AND, OR, NAND, and NOR gates VLSI Design II: VHDL

  22. Definitions • Test generation algorithms work in terms of: • Primary inputs— (PI) a controllable input to a circuit. E.g., a pin on an IC, or an output of an FF in a scan system • Primary outputs— (PO) an observable output of the circuit. E.g., a pin on an IC, or a D input to an FF in a scan system • Justify, justification— the process of selecting PIs to force a certain line to have a specific value • Propagate, propagation— the process of selecting appropriate PIs that allow a discrepancy “D” to be pushed to a PO • Test generation algorithms are all about • finding the appropriate PIs to control to activate a fault • finding the appropriate PIs to control to propagate the fault to one of the POs. VLSI Design II: VHDL

  23. More Definitions • Forward implication • Def:Knowing one or more gate inputs, imply the output value. • Assume all gate inputs are the same value — either all c or all c’ • Then the output is output = value  i • We can refine this if we know the controlling value • i.e. only one of the inputs needs to have c to know output • Backward implication • Def:Knowing the output and possibly some inputs, imply one or more of the inputs • Assume all gate inputs are the same — either all c or c’ • Then the inputs are: inputs = output  i • We can refine this if we know the controlling value • If the input needed to produce the output is c, then only one input needs to have it. VLSI Design II: VHDL

  24. x 1 0 l 0 1 1 l Justify Algorithm • Justify (l , v) — Recursive algorithm to justify line l to value v l = v if l is a primary input return — you’re done on this path set c and i to controlling/inversion values of gate driving l inval = v  i if (inval == c) select one input j of gate l Justify (j, inval) else for every input j of gate l Justify (j, inval) VLSI Design II: VHDL

  25. justify a to 1 a B PO An example of justification l = v if l is a primary input return — you’re done on this path set c and i to controlling/inversion values of gate driving l inval = v  i if (inval == c) select one input j of gate l Justify (j, inval) else for every input j of gate l Justify (j, inval) VLSI Design II: VHDL

  26. l k Justify enabling values onto other inputs Propagate further Test Generation: Propagate Algorithm • Prop (l , err) — Propagate value err from line l l = err if line l is a primary output return — you’re home k = fanout gate of line l c,i = controlling/inversion value of gate k for every input j of k other than l Justify (j, c’) Propagate (k, err  i) VLSI Design II: VHDL

  27. Testing Digital Circuits • What you know • Fault models — what can go wrong and how we model it • physical and logical • Basic idea of detection — activate fault and propagate to output • What you don’t know • how to figure out, systematically, whether the whole thing works • how to reduce the number of faults to consider when generating tests • Today • Review equivalence and fault collapsing • Begin test generation algorithms VLSI Design II: VHDL

  28. Detection • Basic approach seen so far • Select a line and a fault — line l s-a-v • Activate the fault • Drive line l to v’ — selecting the inputs needed to set an internal line to a known value is known as line justification • Activation creates a discrepancy “D” • Propagate the fault • Propagate the discrepancy D along a sensitized path to any primary output discrepancy s-a-0 0 1/0 Notation: good value/bad value x 0/1 1 VLSI Design II: VHDL

  29. Fault Dominance • Equivalence vs. Dominance • Dominance is a special case of fault equivalence • Fault equivalence, if Z f (x) = Z g (x) for all xthen the faults are functionally equivalent. • If this is true for a subset of x, then there is a dominance relation • Dominance • Let Tg be the set of all tests that detect a fault g. • A fault f dominates the fault g iff f and g are functionally equivalent under Tg. Z f (t) = Z g (t) for all t in Tg • Tg is a subset of Tf VLSI Design II: VHDL

  30. Equivalence and Dominance Summary • What are the equivalence classes? s-a-0 s-a-1 Equivalence A0, B0, Z1 s-a-0 s-a-1 s-a-0 s-a-1 Dominance Z0 dominates A1, B1 11, 01, 10 VLSI Design II: VHDL

  31. Tg 10 01 00 Tf Aside: Fault Location • Detection got us down to three tests • We’re left with three tests for this gate if we’re interested in fault detection. • If we’re interested in fault location, we need more • To isolate y s-a-1 • Need to apply both 10 and 01 • 10, alone, detects the equivalent faults y s-a-1 and z s-a-0 • 01, alone, detects the equivalent faults x s-a-1 and z s-a-0 • Together, they can isolate the three faults (assuming only one fault active). x sa1 z sa0 y sa1 VLSI Design II: VHDL

  32. define fault model select target fault no more faults: done generate test for target fault simulate discard detected faults Overall process set of faults for circuit VLSI Design II: VHDL

  33. Test Generation • Toward an algorithmic means to generate test vectors • What do we want in a test vector? • fault activation and propagation • if the discrepancy D wiggles (i.e. from good to bad), then so does the output • how do we determine if a function changes with respect to a variable • Use Automatic Test Generation algorithms (ATG) VLSI Design II: VHDL

  34. Primary inputs and outputs • Test generation algorithms work in terms of: • Primary inputs— (PI) a controllable input to a circuit. E.g. A pin on an IC, or an output of an FF in a scan system • Primary outputs— (PO) an observable output of the circuit. E.g. A pin on an IC, or a D input to an FF in a scan system • They all operate in terms of: • finding the appropriate PIs to control to activate a fault • finding the appropriate PIs to control to propagate a discrepancy to one of the POs. VLSI Design II: VHDL

  35. a B PO PIs Propagate, Justify • A few definitions • justify, justification— the process of selecting PIs to force a certain line to have a specific value • the verb … justify a 0 on the input a of gate B • the noun … justification is the process of justifying • propagate, propagation— the process of selecting appropriate PIs that allow a discrepancy “D” to be pushed to a PO • … propagate the D to any output • … propagation is the process • involves justification VLSI Design II: VHDL

  36. Imply all you can… • Forward implication • Def:Knowing one or more gate inputs, imply the output value. • Assume all gate inputs are the same value — either all c or all c’ • Then the output is output = value  i • We can refine this if we know the controlling value • i.e. only one of the inputs needs to have c to know output VLSI Design II: VHDL

  37. Look behind yourself too… • Backward implication • Def:Knowing the output and possibly some inputs, imply one or more of the inputs • Assume all gate inputs are the same — either all c or c’ • Then the inputs are: inputs = output  i • We can refine this if we know the controlling value • If the input needed to produce the output is c, then only one input needs to have it. VLSI Design II: VHDL

  38. x 1 0 l 0 1 1 l Justify Algorithm • Justify (l , v) — Recursive algorithm to justify line l to value v l = v if l is a primary input return — you’re done on this path set c and i to controlling/inversion values of gate driving l inval = v  i if (inval == c) select one input j of gate l Justify (j, inval) else for every input j of gate l Justify (j, inval) VLSI Design II: VHDL

  39. justify a to 1 a B PO An example of justification l = v if l is a primary input return — you’re done on this path set c and i to controlling/inversion values of gate driving l inval = v  i if (inval == c) select one input j of gate l Justify (j, inval) else for every input j of gate l Justify (j, inval) VLSI Design II: VHDL

  40. l k Justify enabling values onto other inputs Propagate further Test Generation: Propagate Algorithm • Prop (l , err) — Propagate value err from line l l = err if line l is a primary output return — you’re home k = fanout gate of line l c,i = controlling/inversion value of gate k for every input j of k other than l Justify (j, c’) Propagate (k, err  i) VLSI Design II: VHDL

  41. x2 x3 x1 Z x5 x4 Will this always work? • Will justify and propagate always work? • Circuits without reconvergent fanout • “select one” and “justify” are each independent of any previous justification • you’re guaranteed that propagation and justify will not interfere VLSI Design II: VHDL

  42. Will require more justification x2 s-a-0 x3 x1 Z x5 x4 Test Generation: Basic Algorithm • Algorithm to test line l s-a-v begin set all values to x (unknown) Justify line l to value v’ if (v == 0) Propagate D on line l else Propagate D’ on line l end VLSI Design II: VHDL

  43. Automatic Test-Pattern Generation (ATPG) • Test U2.ZN for s-a-1 • 1) Activate (excite) fault =>U2.ZN = 0 • 2) Work backward => A = 0 • 3) Work forward (sensitize the path to PO) =>U3.A2 = 1, U5.A2 = 1 • 4) Work backward (justify outputs) =>ABC = 110 VLSI Design II: VHDL

  44. Reconvergent Fanout Fault B s-a-1? Fault U4.A1 s-a-1? We create two sensitized paths that prevent fault from propagating to the PO. The problem can be solved by changing A to 0, but this breaks rules of the ATPG! The PODEM algorithm solves the problem. Signal B branches and then reconverges at logic gate U5. ATPG works. VLSI Design II: VHDL

  45. d G2 G4 a s-a-1 D’ b G1 c G5 G3 e Test Generation — example • With reconvergent fanout • Fanout paths from a gate reconverge at some later gate • Inputs needed for propagation may be inconsistent with ones needed for justification Procedure: justify G1 to 0 —> a=b=c=1 propagate to G4 —> requires G2 = 1 but a=1 makes G2=0 Inconsistency— crash and burn Kaboom! VLSI Design II: VHDL

  46. Procedure: justify G1 to 0 —> a=b=c=1 propagate to G4 —> requires G2 = 1 but a=1 makes G2=0 Inconsistency propagate to G5 —> justify G3 to 1 this works with e=0 d G2 G4 a s-a-1 D’ backtrack b G1 c G5 G3 e Test generation — example, cont’d • Need to backtrack — propagate on other path VLSI Design II: VHDL

  47. State 1 State 1B State 1A win State 1A1 State 1A2 fail fail Backtracking • Backtracking requires that a decision tree be maintained • Each node describes a design’s state • values previously justified on lines • implications, forward and backward • Each arc describes a new decision • justify a line, activate a fault • Need to be able to go back… • to former state VLSI Design II: VHDL

  48. backtrack Maintaining the decision tree Procedure: justify G1 to 0 —> a=b=c=1 propagate to G4 —> requires G2 = 1 but a=1 makes G2=0 Inconsistency propagate to G5 —> justify G3 to 1 this works with e=0 State 1 all x’s justify G1 to 0 State 1A a=b=c=1 Prop. to G5 Prop. to G4 G3 = 1 e = 0 win G2=1, a=1 inconsistency fail State 1A1 State 1A2 Backtrack, G2=1 no longer part of design state. Revert to previous state. VLSI Design II: VHDL

  49. Observations on approach • Enumeration used • justify algorithm was recursive • When gate has controlling value on input, one path selected • may need to backtrack and follow another • eventually, may need to follow all • Propagate algorithm was recursive • When there is a fanout at a propagation point, one path selected toward output • may need to backtrack and follow another • eventually, may need to follow all • The backtracking, again, is due to reconvergent fanouts and previous values justified on them • No solution? — redundant wrt the fault • As it turns out… • The natural state maintenance in recursive programs can keep track of the decision tree VLSI Design II: VHDL

  50. x D’ x x D-frontier More terminology • When propagating a discrepancy • Often, due to fanout, there are several options • Propagate needs to pick one for the sensitized path • D - frontier • The D-frontier is the set of all gates with D or D’ on one or more inputs and an x on its output (no other inputs are controlling) • This is the set from which you select a propagation (sensitization) path VLSI Design II: VHDL

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