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Combinational Logic and Verilog

Combinational Logic and Verilog. Programmable Array Logic PAL. Example of PAL. GAL16V8C. PALs. SOP Multi-level Flip-flops 10 Inputs 8 Inputs/output. Figure 6-26. PAL16L8. Figure 6-28. General CPLD architecture. Complex PLD. 4*3 PLA in CMOS logic. EEPLDs. Floating gate

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Combinational Logic and Verilog

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  1. Combinational Logic and Verilog

  2. Programmable Array Logic PAL

  3. Example of PAL. GAL16V8C

  4. PALs • SOP • Multi-level • Flip-flops • 10 Inputs • 8 Inputs/output Figure 6-26. PAL16L8

  5. Figure 6-28. General CPLD architecture Complex PLD

  6. 4*3 PLA in CMOS logic

  7. EEPLDs • Floating gate • Non-floating gate AND plane of EEPLD using floating-gate MOS transistors

  8. Decoders

  9. General Structure of a Decoder circuit

  10. Example 1: Truth table for a 2-to-4 binary decoder. Example of a decoder circuit enable

  11. 2-to-4 decoder inside enable

  12. Verilog for 2-to-4 decoder Structural type of description in Verilog

  13. Example 2:Position encoding for a 3-bit mechanical encoding disk

  14. Example 2 continued: Using a 3-to-8 decoder to decode a Gray code.

  15. Example 3: 74x138 3-to-8 decoder

  16. Example 3: 74x138 3-to-8 decoder

  17. Example 3 cont: 74X138 3-to-8 decoder

  18. Verilog code for 3-to-8 decoder 15..7

  19. Verilog for 3-to-8 decoder Y_L[0] Y_L[1] Y_L[2] Y_L[3] Y_L[4] Y_L[5] Y_L[7] A[2] A[1] A[0]

  20. 74X138 Decoder: Active level handling

  21. 74x138 like decoder with Active level handling

  22. Active high 3-to-8 decoder

  23. Behavioral Verilog for 3-to-8 decoder

  24. Example 3 cont:74x138 3-to-8 decoder Default signal names

  25. Example 3 cont:Symbols for 74x138 Incorrect because of double negations

  26. Example 3 cont:5-to-32 decoder from 74X138 chips Chip select goes to input G2B Global enable goes to inputs G1 and G2A

  27. Example 3 cont: 4-to-16 decoder using 74X138 N3

  28. Example 3 cont:74x138 decoder using GAL 74x138 decoder can be built in single GAL 16V8 chip

  29. Figure 6-41. 74x138-like decoder

  30. Example: Customized decoder function

  31. Customized decoder circuit Using 74X138

  32. Seven Segment Display and Decoder

  33. Seven Segment Display

  34. Seven Segment Decoder

  35. Encoders We already used encoders to design control logic for data path blocks

  36. Encoders 2n requests

  37. Priority Encoders

  38. Encoders Number n of prioritized request Any subset if 2n requests

  39. Encoders

  40. 8-input Priority Encoder enable

  41. 15-input Priority Encoder in PLD outputs inputs

  42. Priority Encoder – handle 32 requests

  43. 8-input Priority Encoder

  44. Three state Buffers

  45. Various three-state buffers

  46. Use of three-state buffers Eight sources sharing a three-state party line

  47. Timing diagram for the three-state party line

  48. 74x541 Octal three-state buffer

  49. Three-State buffers in microprocessors

  50. 74x541 as a microprocessor input port.

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