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Threshold. Baseline. Reset. Reset. Zoom-in. After detecting rising-edge of comparator, count x (in this case 5) clock pulses, then enable ADC. Assuming 800 kcps , the ADC takes 1.25 μ s to sample. Timing Diagram. 1 horizontal unit = 5 clock cycles = 250 ns. Positive edge-triggered.
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Threshold Baseline Reset Reset Zoom-in After detecting rising-edge of comparator, count x (in this case 5) clock pulses, then enable ADC Assuming 800 kcps, the ADC takes 1.25 μs to sample Timing Diagram 1 horizontal unit = 5 clock cycles = 250 ns
Positive edge-triggered Count 5 clock cycles before starting ADC Reasons for a Flip-flop • Prevents system from paralyzing • A 2nd data sampling cycle can’t begin in the midst of the 1st • Anything else?
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Group Tasks 4 Knobs 1) Input gain 2) Threshold voltage 3) Time-to-sample 4) Coincidence, anti-coincidence, and no coincidence • Test/fix the detector, pre-amplifier, and shaping-amplifier • Look at the pulses coming from the X-ray source