1 / 15

Team DC-HSBA

This project focuses on the design and implementation of an embedded software graphics accelerator, specifically a media-centric co-processor capable of high floating-point computation performance. Utilizing Cyclone III FPGAs and 512MBit DDR SDRAM, the hardware includes a complete graphics pipeline demonstration on an FPGA development board. The project encompasses custom caches, communication methods, and a main user interface, along with the development of a Tetrisphere clone game. Key team members will oversee various aspects including logic design, board design, and software development.

mareo
Download Presentation

Team DC-HSBA

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Team DC-HSBA David Hover Jonathan Tate Robert Benson Paul Niewoonder

  2. Primary Goal • Embedded Software Graphics Accelerator • Shader Unit • Media-Centric Co-Processor • High Floating-Point Computation Performance • Graphical Computation • Complete Software Graphics Pipeline

  3. Demonstration Hardware • FPGA Board • Outputs • Monitor • LEDs • Inputs • Programming Inputs (JTAG) • Buttons • Knobs

  4. Demonstration Software • Main User Interface • Benchmarks • Demos • Game • Tetrisphere Clone

  5. Approach

  6. Implementation • Hardware • Cyclone III FPGAs • DDR SDRAM (512MBit) • Tricolor LEDs • Serial Programming Device (EPCS) • DAC • 8 Directional Joystick

  7. Implementation (cont.) • Communication Methods • DDR For FPGA/Memory • LVDS For FPGA/FPGA • Software • Assembler • OpenGL Like

  8. Implementation (cont.) • Logic • Prebuilt • SOPC Builder • Memory Controllers • NIOS • Custom • Caches • LVDS to AVALON Bridge • Shader

  9. Preliminary Cost Estimate

  10. Schedule

  11. Division of Labor • Jonathan Tate • Lead Designer • Logic Design • Graphics Pipeline • David Hover • Assembler • User Application Software • Robert Benson • Administrator • Board Design • User Application Software • Paul Niewoonder • Logic Design • Case • Graphics Pipeline

  12. Risks and Contingencies • Medium Risk • Lobster Requires >2 Revisions • Parallel Design The Larger Boards • Remove Them From Design • Low Risk • Lobster Requires >4 Revisions • FPGA Development Board • Critical Design Flaw – Leg • Quick Redesign – Fit Single FPGA • Critical Design Flaw – Shader • Quick Redesign - Software Use NIOS Only

  13. Risks and Contingencies (cont.) • Low Risk (cont.) • Damaged Board Night Before • FPGA Development Board • Pre-Prepped Backup • Funds Shortage • Project Designed Around Budget • Donations or Student Discounts • Remove Functionality/Parts • Additional Contributions From Team

  14. Risks and Contingencies (cont.) • Low Risk (cont.) • Shipping Errors • Order Early • Parts Availability • Order Early • Redesign If Necessary • Team Member Unavailability • Schedule Allows Short Absence

  15. QUESTIONS?

More Related