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Adding the Superset Adder to the DesignWare IP Library

The integration of the Superset Adder into the DesignWare IP Library addresses the growing challenges in technology scaling, emphasizing redundancy, error detection, and correction in memory circuits. As the demand for reliable arithmetic datapaths increases, the design focuses on redundancy and reconfiguration strategies to meet these needs. This document delves into the performance of various addition circuits like Kogge-Stone and Brent-Kung, analyzing their delay, area, and power efficiency. It also guides integration with Synopsys Design Compiler and VHDL outputs for optimal performance.

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Adding the Superset Adder to the DesignWare IP Library

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  1. Adding the Superset Adder to the DesignWare IP Library Stevo Bailey

  2. Motivation Technology scaling exacerbates variation and reliability issues Memory circuits have redundancy and error detection/correction schemes Need arises for robust arithmetic datapaths Redundancy, reconfiguration

  3. Addition in Circuits A3 B3 A2 B2 A1 B1 A0 B0 Cin A3 B3 A2 B2 A1 B1 A0 B0 Setup FA G3 P3 G2 P2 G1 P1 G0 P0 FA FA G3:2 P3:2 G1:0 P1:0 FA CLA (Prefix) Blocks Cout S3 S2 S1 S0 Ripple Carry Addition Delay: O(N) G3:0 P3:0 Minimum Parallel Prefix Delay: O(log2N) Prefix Operation: Sum Calculation (not shown): (G1:0, P1:0) = (G1 + P1G0, P1P0) Si = Gi-1:0 XOR Pi

  4. Parallel Prefix Adders Kogge-Stone Brent-Kung Han-Carlson Trade logic depth (delay) for complexity (area and power) Radix 2, fan-in 2

  5. Superset Adder Full Tree Full controllability over prefix nodes

  6. Synopsys Overview Module Compiler Code Module Compiler Optimized VHDL Add to DC Synthetic Library Path Synthetic Library Code Analyze VHDL in DC

  7. Module Compiler Input and Synthesis MCL Code Module Compiler Analysis

  8. Module Compiler Output Module Compiler Output Files Module Compiler Output VHDL

  9. Module Compiler Relative Placement Relative Placement View (manual)

  10. Area Comparison

  11. Delay Comparison

  12. Design Compiler Code TCL Script Synthetic Library Code

  13. Design Compiler 8-bit Superset Adder Schematic

  14. Design Compiler 8-bit Superset Adder Schematic

  15. Current Issue How do I get VCS to simulate my adders when they include library components?

  16. Questions?

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