Download
1 / 4
40 likes | 175 Views
This lab guide provides a detailed walkthrough for integrating peripherals into an existing processor system using the IP Catalog in XPS. You'll modify an MHS file, create design netlists with Platform Generator, and generate a bitstream using ISE. By the end of this module, you will have gained the skills to add additional IP to your hardware design and implement it using ISE. This includes adding GPIO cores and SW code to read DIP switches and push buttons, displaying results on HyperTerminal, and utilizing various bus systems like OPB, PLB, and UART.
E N D
Adding IP to a Hardware Design Lab 2 Introduction This material exempt per Department of Commerce license exception TSU
Introduction • This lab guides you through the process of adding peripherals to an existing processor system via the IP Catalog in XPS. • An MHS file will be modified, and design netlists will be created via Platform Generator • The bitstream will be generated from ISE
Objectives After completing this module, you will be able to: • Add additional IP to a hardware design • Implement the design by utilizing ISE
Add GPIO Cores Add SW code to read state of DIP switches and Push Buttons and display on hyperterm OPB Bus PLB Bus UART GPIO DIP Switches PLB2OPB PPC GPIO Push Buttons PLB BRAM Cntlr PLB BRAM MY IP LEDs PLB BRAM Cntlr PLB BRAM Timer INTC ICON IBA
