1 / 7

IP Library

IP Library. Dr Stephen Bell Rutherford Appleton Laboratory 18/12/2013. IP library -development and management. What is required for an IP Library :. Documentation! Documentation! Documentation! EDA library database Common standard for designing of IP blocks Core supported tools set

oni
Download Presentation

IP Library

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. IP Library Dr Stephen Bell Rutherford Appleton Laboratory 18/12/2013

  2. IP library -development and management What is required for an IP Library: • Documentation! Documentation! Documentation! • EDA library database • Common standard for designing of IP blocks • Core supported tools set • Acceptance criteria and peer review • Revision control • Storage and access

  3. EDA library database EDA library database should contain: • Description of block and it’s function • Specification of IP across PVT corners • Design database cell views and textual files • Layout pinout/placement details (Hardblocks) • Test benches to simulate/verify • Synthesis/P&R scripts (Softblocks) • Datasheets (Waveforms/measurements)

  4. EDA library database-analogue focused • Block cell views: schematic/layout/symbol/verilog(a/ams)/config/abstract • Test benches used to characterised IP block • Multi-testbench simulation environment: adexl • Datasheet with simulation results automatically generated from ADEXL • Files • Liberty black box model(pin info/antenna) • Verilog model(black box) • Spice subcircuit (Pre/post-layout) for fast spice modelling • LEF file for standalone P&R environment • GDSII and layers file

  5. IP library structure Open Access IPLibrary Cell level IP_BlockTB_AC IP_BlockTB_TRAN .. IP_Block View level schematic schematic schematic constraints config config verilogA/AMS configPS .. symbol configAMS layout config= netlist view list control configPS=netlist for post layout configAMS= netlist for simulator extracted ADEXL Refs testbenches State files

  6. Parameters for Circuit Opt. ADEXL view Corners set for PVT Multi-test env. Auto. gen. datasheets Documentation ADEXL Specifications State files Yield analysis

  7. Conclusions ADE XL/GXL provides: • Central location for storing simulation results and documentation • Automatic generation of datasheets • Specification driven environment • Platform for retargeting/optimisation IP blocks

More Related