2005 updates to the Lithography chapter of the ITRS

1. 2005 updates to the Lithography chapter of the ITRS Lithography International Technology Working Group December 2005 Presented by Scott Hector; Freescale Semiconductor, Inc.

2. Lithography ITWG chair persons and co-chair persons for 2005

3. 2005 Lithography Updates • CD control and line edge roughness (LER) • Agreed along with Design, PIDS and FEP TWGs to increase CD tolerance to 12% for MPU gates • CD control for MPU gates is still red (red starts at <4 nm 3) • Agreed with FEP TWG on larger printed CD in resist • 1.6818physical gate length and 75%/25% CD variance allocation for lithography and etch, respectively • Updated definition of LWR and values for low frequency LWR • Increased bias between size in resist and after etch to +10% for contacts • Significantly tightened overlay tolerances from 35% to 20% of flash/DRAM ½ pitch • Updated potential solutions • Updated colors and values in mask and resist tables • Added table describing imprint template requirements • Identified requirements for exposure tool fluids and environment (included in Yield chapter)

4. 2005 ITRS lithography requirements Not an official ITRS table

5. Difficult challenges ≥ 32-nm ½ pitch

6. Difficult challenges ≥ 32-nm ½ pitch

7. Difficult challenges < 32-nm ½ pitch

8. Significant changes to potential solutions in 2005 • 193nm immersion with water and other fluids expected to be primary technology through 45nm and perhaps 32nm ½ pitch with new materials for final lens element • 157nm no longer anticipated as potential solution • EUV remains most likely next generation lithography (NGL) with possible use starting at 45nm ½ pitch and primary solution for 32nm and 22nm ½ pitch • Electron projection and proximity electron no longer anticipated as potential solutions • Maskless lithography remains as potential solution starting at 45nm ½ pitch • Imprint extended to cover 32nm through 16nm ½ pitch

9. 65 45 32 22 16 Potential solutions for lithography

10. 140 2001 Edition 2003 Edition 130@2001 120 100 90 90@2004 193nm+PSM 80 70 65@2007 193nm 60 50 PEL 45@2010 40 193nm+RET+LFD+Immersion PEL IPL PXL ML2 EUV EPL 32@2013 EPL 30 193nm Immersion 157nm+RET+LFD+Immersion EUV 193i w/ other fluids EUV ML2 ML2 Imprint Imprint 22@2016 20 +RET Innovation Innovation Innovation History of ITRS Litho Potential Solutions 2005 Edition 248nm+PSM 157nm+PSM Acknowledge: Kameyama, Nikon

11. Resolution improvement by immersion Lens Lens q Liquid Photoresist Photoresist Silicon Wafer Silicon Wafer nwater = 1.44

12. Enabling NA > 1.3 for <45-nm ½ pitch Numerical aperture 1.3 1.4 1.5 1.6 1.7 Water High Index Fluid Immersion Fluid High Index Lens Material Plano CaF2or SiO2 Final Lens Element Curved Final Element Existing Platforms High Index Resist Resist Possible numerical aperture determined by minimum index of refraction among the fluid, final lens element and resist Acknowledge: Andrew Grenville

13. 80 Ref. (%) 0 12.0 13.0 14.0 l (nm) Extreme Ultraviolet Lithography(EUV) Ring Field Illumination Scanning mask and wafer stages Flat, square mask with multilayers l = 13.5 nm Reflective Reticle Laser Produced Plasma* All optics surfaces coated with multilayer reflectors (40 - 80 layer pairs, each layer approx l/4 thick, Control ~0.1 Å) Laser 40 Condenser Optics 4X Reduction Optics * An electric discharge source might also be used Wafer EUV imaging with ultrathin resist (UTR) 70nm 35nm Reflective Optical Surfaces are Aspheric with Surface Figures & Roughness < 3 Å

14. 2005 updates to the chapter text • Added table showing progression of low k1 methods and lithography friendly design • DFM description to complement content in Design chapter • Automatic process control (APC) detail • Cost of ownership factors and throughput factors described in text • Brief text about number of critical levels

15. Evolution of low-k1 lithography

16. w/ rework Product Yield NO Rework Cost of Ownership Overview Significant CoO impacts with very low system throughput and low mask usage Source: Phil Seidel, SEMATECH

17. Changes to ITRS Resist Tables • Re-evaluated all colors in resist tables • Input from resist suppliers toward matching capability (colors) with requirements (numbers) • Re-examined defect size in resist films • Back surface particle levels updated based on FEP values • Improved LWR/LER definition and values

18. Poly rs Rough Gate Edge Gate-SD Overlap disorder Gate n+ n+ Junction edge fluctuations Halo fluctuations Areas of potential device impact for LER • Front end patterning • LWR after etch is what matters, not LWR in resist • LWR affects leakage current more strongly than drive current Fringing Field Disorder Nominal device w/o LER L=32nm Ioff ( nA / um on log scale ) L=40nm 7nm 3s LER L=50nm Ion ( uA / um ) Eric Verret, Aaron Thean and Jonathan Cobb; Freescale Semiconductor

19. Importance of Line Edge and Width Roughness Example: poly-silicon line • Line Edge Roughness (LER) (High frequency roughness) • Can affect dopant concentration profiles • Probably affects interconnect resistance • Line Width Roughness (LWR) (Mid-frequency roughness) • Leakage of transistors affected • Affects device speed of individual transistors • Leads to IC timing issues Edge assignment from SEM algorithm Low High Spatial frequency (nm-1) Ben Bunday, SEMATECH

20. Bare fused silica Patterned MoSiN or CrON attenuator with AR coating 4X Mask Pellicle EUV mask 193nm mask Imprint template 4X Mask 1X Mask Comparison of EUV, 193nm and imprint masks Relief pattern in fused silica (no pellicle) Mo/Si multilayer with capping layer Patterned Ta-based absorber with AR coating (no pellicle) • 2.7 nm 3 / 4.8 nm 3 1.3 nm 3 / 4.8 nm 31.7 nm 3 / 2.7 nm 3 • ITRS 2005 mask CD uniformity / pattern placement requirements for 45nm ½ pitch MPU Acknowledge: Chuck Gwyn, Intel; EUV Symposium 2003

21. Scaling relations for Table 77 and 79 ItemValue (in nm) where becomes: YellowRed CD = Physical gate width = 0.4  DRAM ½ pitch 40 20 Overlay = 20%  DRAM ½ pitch 20 11 Minimum linewidth in resist = 1.6818  physical gate 50 25 Contact size after etch = 1.125  ½ pitch 85 60 Contact in resist = 1.1  contact after etch 75 50 CD control for DRAM = 13.5%  sqrt(0.75)  DRAM ½ pitch 7 4 CD control for MPU/ASIC = 7 4 12%  sqrt(0.75)  MPU/ASIC M1 contacted ½ pitch Mask nominal image size = MAG  resist linewidth 200 130 SRAF feature is ½ of mask nominal image 130 100 Mask Min. Primary Feature Size = 200 130 0.7  Mask nominal image size Mask CD control = CD  MAG  sqrt(0.75)  4% / MEEF 8 5 Placement = Overlay  MAG  15% 14 10 Defect size = DRAM ½ Pitch  MAG / 5 80 60 Linearity = 3.8%  DRAM ½ pitch  MAG 15 10 CD mean-to-target = 2%  DRAM ½ pitch  MAG 7 4 Absorber LER = Min. CD  MAG  3% 7 4 Blank flatness  1/NA2 (250nm in 2007) 250 150 Data volume = 2 increase / node (260 GB in 2004) 260 5000 GB Not an official table in ITRS

22. Summary • 193nm immersion and EUV lithography are promising candidate technologies for 45-nm and 32-nm half-pitch patterning • Significant challenges remain in developing either technology to provide a timely, economical manufacturing solution • Innovative immersion, EUV and new techniques such as ML2 and imprint might become prevalent starting at 32-nm ½ pitch • Maintaining ±10% CD control doesn’t appear to be possible, and ±12% adopted, ±12% still difficult to achieve • More stringent overlay tolerances (20% rather than 35% of half pitch) important for manufacturing of memory circuits • Measuring and controlling LWR and LER becoming increasingly important • Increasing integration of design, modeling, lithographic resolution enhancement techniques and extensive metrology will be needed to maintain expected circuit performance