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2005 ITRS ORTC Product Technology Trends. ITRS/IRC Tokyo 11/30/04 Alan Allan Rev 2. 2004 (2004 ITRS Exec. Summary and ORTC”) – it’s all about:. Economics + Technology…and Customers , who Buy Electronic Products (~$1T) (emulated and mapped to chips)

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2005 ITRS ORTC Product Technology Trends


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    1. 2005 ITRS ORTCProduct Technology Trends ITRS/IRC Tokyo 11/30/04 Alan Allan Rev 2 Work in Progress – Do Not Publish

    2. 2004(2004 ITRS Exec. Summary and ORTC”) – it’s all about: • Economics + Technology…and • Customers, who Buy • Electronic Products (~$1T)(emulated and mapped to chips) • Which are Needed to ENABLE Services (~$5T) • Which, though the customers don’t know or appreciate it, need ENABLING bySemiconductor Chips (~$0.2T) Manufacturing, ENABLED byEquipment (~$0.04) and Materials (~0.02B) all of the above ENABLED by: • Nodes • Chip Sizes • Transistors • Capacity • $ Work in Progress – Do Not Publish

    3. 90’s 21st Century Technology Economics Semiconductor Industry Semiconductor Industry Clear Both Economics + Technology Hurdles = Growth Work in Progress – Do Not Publish

    4. Global & Regional Political & Macro-Economic Environments …and who BUY, based on varying levels of Purchasing Power, PRODUCTS Electronic End Equipment Semiconductors Customer Demand Semiconductor Equipment Materials Ecosystem or Foodchain? Semiconductor & Equipment Materials Sources: NASA.gov ; SEMI Wanted: CUSTOMERS, who breathe, eat, and live in….. Work in Progress – Do Not Publish

    5. SERVICES (new drivers) Traditional (drivers) • Internet service providers • Communication services • Broadcasters • Computer • Consumer • Automotive • Communications • Industrial / Medical • Defense / Aerospace $5000B $1000B • Electronic industry $166B • Semiconductor industry SUPPORT INDUSTRIES “Fab” equipment $28B Materials $21B EDA $3B Source: STMicroelectronics (2003 data) Semiconductors is the ‘key enabler’ for wealth creation Work in Progress – Do Not Publish

    6. Drivers: Services (~$5T), enabled by: Drivers: Electronic Products (~$1T) 4% 6% 35% 16% 16% 9% 14% $40B* $65B* $379B* $176B* $175B* $92B* [$150B**] Applications (NEMI) Computer & Consumer & Military & Medical Automotive Office Network Defense Portable [Industrial] Communications SIP/SOC (ITRS) SIP/SOC A4 A3 A2 A1 Architectures Chips /Fabrics (ITRS) MPU Memory DSP AMS Source: ITRS Design TWG Figure 1: Potential mapping approach between NEMI and ITRS roadmaps *Source: NEMI/Prismark, ca. May’04 ** VLSIR ca Sep’04 Work in Progress – Do Not Publish

    7. Figure 2: Illustration of potential references between NEMI and ITRS roadmaps Work in Progress – Do Not Publish

    8. Transistors - Tx Tx/chip (Tx/cm2) Moore’s Law Functional Cost - $/Tx Log (Arbitrary Units) Revenue Capital Investment R&D Investment Mfg Cost - $/cm2 1960 1970 1980 1990 2000 2010 2020 SEMICONDUCTOR Industry Economics – Basic View Work in Progress – Do Not Publish

    9. Demand Results Improving Densities Work in Progress – Do Not Publish

    10. Industry Capacity Results Work in Progress – Do Not Publish

    11. 3-year Node Cycle Past - Future hp 5760 hp 4080 hp 2880 hp 2040 hp 1440 hp 1020 hp 720 hp 510 hp 360 hp 255 hp 180 hp 130 hp 90 hp65 hp45 hp32 hp22 hp16 Scenario C: 3(thru 250nm)-2(thru 90nm)-3 Scenario D: 3(thru 250nm)-2(thru 45nm)-3 hp 90 hp 65 hp 45 hp32 hp22 hp16 hp11 [Proposal] 2005 ITRS Flash Proposal: Sc.C = Catch DRAM @ 2004/90nm; then 3-yr cycle Sc.D = Cross-over DRAM @ 2004/90nm; then 2-yr cycle to 2006/65nm and 2008/45nm; then 3-yr cycle 1-year Node Cycle Scenario D: 2-year Node Cycle: DRAM from 1998-2004 Flash from 2004-2008 3-year Node Cycle 2-year Node Cycle Samsung “60nm” 8Gbit/0.008u2/bit[MLC]; Est. 4Gbit 0.016u2/cell[SLC] Intro/2004; est. Prod/2005-7 2005-2020 ITRS Range Work in Progress – Do Not Publish

    12. Work in Progress – Do Not Publish

    13. 26% CAGR Litho ~3% CAGR Design = ~29% CAGR density 26% CAGR Litho ~0% CAGR Design ~29% CAGR density [w/Actual History] Work in Progress – Do Not Publish

    14. 26% CAGR Litho ~3% CAGR Design = ~29% CAGR density 26% CAGR Litho ~0% CAGR Design ~29% CAGR density [+Adjustment for History + 2005 Proposal Sc.C – Unchanged; MPU Density Tracks IEM] Work in Progress – Do Not Publish

    15. ITRS Sc.C:Prior 1998/255nm DRAM / 3-year Node: 26.0% Litho Improvement x 12.2% Design Factor Improvement = 41.4% Density Improvement ITRS Sc.C:1998/255nm–2004/90nm DRAM / 2-year Node: 41.4% Litho Improvement x 0% Design Factor (flat@8) Improvement = 41.4% Density Improvement ITRS Sc.C:2004/90nm–2022/11nm DRAM / 3-year Node: 26.0% Litho Improvement x ~2.6% Design Factor (Ave8-5) Improvement = 29.3% Density Improvement ITRS Sc.C:Prior 1998/255nm MPU / 3-year Node: 26.0% Litho Improvement x 0% Design Factor Improvement = 26.0% Density Improvement ITRS Sc.C:1998/255nm–2004/90nm MPU / 2-year Node: 41.4% Litho Improvement x 0% Design Factor Improvement = 41.4% Density Improvement ITRS Sc.C:2004/90nm–2022/11nm MPU / 3-year Node: 26.0% Litho Improvement x 0% Design Factor Improvement = 26.0% Density Improvement Product Density (Roadmap C) 26% CAGR Litho ~3% CAGR Design = ~29% CAGR density Work in Progress – Do Not Publish

    16. [Proposal] Flash Cell Size Proposal: 2x/yr 64Mbit/’99 - 4Gbit/’05 Then 2x/3years 4Gbit/’05 – 128Gbit/’20 Samsung “60nm” 8Gbit 0.008u2/bit[MLC]; Est. 4Gbit 0.016u2/cell[SLC] Intro/2004; est. Prod/2005-7 Work in Progress – Do Not Publish

    17. 2005 ITRS Proposal: 2x/3yrs Flash after 2005 DRAM after 2008 “Moores Law” Ave still 2x/2yrs 1985-2020 [Proposal] 1Tt 2005 ITRS Proposal: 2x/3yrs hp MPU after 2011 cp MPU after 2016 “Moores Law” Ave still 2x/2yrs 1970-2020 1e11t Samsung “60nm” 8Gbit 0.008u2/bit[MLC]; Est. 4Gbit 0.016u2/cell[SLC] Intro/2004; est. Prod/2005-7 2005 ITRS Proposal: “Max Litho” hp < 695mm2 cp < 560mm2 “Moores Law” 2x/2yrs Average 1970-2020 Flash bits/chip Proposal: 2x/yr 64Mbit/’99 - 4Gbit/’05 Then 2x/3years 4Gbit/’05 – 128Gbit/’20 MPU “65nm” High-Performance >1Gt [1 Billion] est. Prod/2005-6 2003/04 ITRS WAS: “Flat Chip-Size” hp = 310mm2 cp = 140mm2 “Affordable” “Moores Law” 2x/Node; After 2001 = 2x/3yrs Yet still Averages 2x/2yrs 1970-2012 “zig-zag” MPU Historical Trend 2000 2000 ITRS MPU Model Start: Hi-Perf .18u 138Mt/1999 Cost-Perf .18u 48Mt/1999 Work in Progress – Do Not Publish

    18. ITRS: 4X/4-6yrs bits/chip; 4X/2.5yrs bits/chip; 4X/4yrs bits/chip; Flat chip size 4X/3yrs bits/chip; 1.414x/3yrs chip size 1971 3”/4” 1981-82 5”/6” 1991-92 200mm 2001-02 300mm 2011-12 450mm 2021-22 675mm Work in Progress – Do Not Publish

    19. MPU Chip size (mm2) – Historical Trends vs Unchanged 2001-03 ITRS Model* 1000 800mm2 Litho Field Size 286mm2 2 per Field Size New: 704mm2 Litho Field Size 572mm2 Litho Field Size 2-yr, 0 chip size growth, then 1.414/1.260 = 12.2% CAGR HP MPU 310mm2 WAS: Node 3yrs, 2x/3yrs = Flat chip @ 1.260x trans/chip/yr Proposed: Node 3yrs, 2x/2yrs, density same @ 1.414x trans/chip/yr CP MPU 140mm2 100 CP Shrink 70mm2 *1999 Leading-Edge .18u CP MPU: 512KB (28Mt [58.3%] x 1.18u2/t = 34mm2) + 20Mt Logic x 5.19u2/t = 104mm2 + 2mm2 OH= 106mm2 = Total 48Mt x ave 2.92u2/t = 140mm2 *1999 Leading- Edge .18u HP MPU: 2MB (113Mt [81.9%] x 1.18u2/t = 135mm2) + 25Mt Logic x 5.19u2/t = 130mm2 + 45mm2 OH= 310mm2 = Total 138Mt x ave 2.25u2/t = 310mm2 * ITRS Design TWG MPU Transistors/Chip Model: ~2x/Node = 2x/2yrs from 1999 - 2001; then 2x/3yrs from 2001- 2016 10 1980 1985 1990 1995 2000 2005 2010 2015 2020 Work in Progress – Do Not Publish

    20. Work in Progress – Do Not Publish

    21. Incl. Flash Model Work in Progress – Do Not Publish

    22. Transistors – VLSI Research May’03 [source: tci030509graphicsSPCL2.xls] ITRS -- Long Term “Moore’s Law” @ 2x/3yrs “Moore’s Law” @ 2x/1.5-2yrs “Moore’s Law” @ 2x/1yr ITRS -- Near Term “Moore’s Law” @ 2x/2yrs Integrated Circuit (IC) … TI & Fairchild ca. 1959 Original G. Moore Paper Electronics, 4/19/65: 2X/1YR “Components Per Integrated Circuit” (aka Functions/Chip) “…That means that by 1975 the number Of components per integrated circuit for Minimum cost will be 65,000…” You are Here! Zeta-Xistors (1e21) Exa-Transistors (Et) 1e18 50Pt [Transistors] Peta-Transistors (Pt) 1e15 2000 1946 1949 2003 2006 1952 2009 1955 2012 1958 2015 1961 2018 1964 1967 2021 Tera-Transistors (Tt) 1e12 1Tt 1e11 2x/3yrs (1G/’05-32G/’20) 1e10 [1971-2019 (1e3)^(1/16yrs) = 54% Ave CAGR] Giga-Transistors (Gt) 1e09 1Gt 1e08 2x/2years 1969 (1K) – 2020 (32G) 1e07 Mega-Transistors (Mt) 1e06 1Mt Transistors/Chip 1e05 ‘05 ‘20 1e04 2005 ITRS Timeframe Kilo-Transistors (Kt) 1e03 1Kt 100 Est. from Semico: 1997 Product Transistors (Pt) Discrete 0.0002 Analog 0.130 Other Memory 0.98 Other Logic 1.78 SubTotal: 2.88 SubTotal: 2.88 MCU 0.84 MPR 0.36 DRAM 42.9 Flash 1.71 MPU 0.78 Total: 49.47 10 Semico (SIA): 1997 Product Units (B) Discrete 197.00 Analog 25.90 Other Memory 3.90 Other Logic 14.80 SubTotal: 241.60 SubTotal: 241.60 MCU 4.20 MPR 1.80 DRAM 3.30 Flash 0.57 MPU 0.26 Total: 251.73 One-a-Transistor (t) 1e00 1t …In the beginning… Bell Labs ca. 1947 Work in Progress – Do Not Publish

    23. [VLSIR ca May’03] Past < -- 2002 ‘02 WAS: [~7.5% CAGR] [~15.5% CAGR] Work in Progress – Do Not Publish

    24. Macro Overview – GWP, Revenue, Capacity Demand Snapshot As of 10/23/02 World Electronics, Semi, Tools, Si Area, #Fabs, Wafer Units vs. GWP ($B) History <- 2000 -> F'cast ‘00 WAS: 1.E+05 $45T 2.8% $10T 1.E+04 USA GDP AVE ~3-4% 4.2% 6-8%? 7.5% $1.1T 1 Tera-Dollar $ 1.E+03 8.26% $.22T $ 1.E+02 (Mu/1e4) $ $.045T 10% CAGR? 7.5-10%? 1.E+01 2010 2020 $ Bilion Dollars ($B); Silicon Sq.In. (Msi/1e4); #Wafers (w / NPW) 47% 2005 15.5 % 1.E+00 47% 29% 5-8%? 1.E-01 10% 15.5 % 1.E-02 1% 0-1%? 1.E-03 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 1976 1958 1960 1962 1964 1966 1968 1970 1972 1974 2006 Source: VLSIR, April, Sept 2001 Tool Sales ($B) Chip Sales ($B) Electronics Sales ($B) GWP ($B) Silicon Sq. Inches (Msi/1e4) Silicon Wafers (Mu/1e4) Total # Fabs (20Kwspm - #/1e04) Work in Progress – Do Not Publish

    25. $ Work in Progress – Do Not Publish

    26. Backup Work in Progress – Do Not Publish

    27. “… http://www.samsung.com/Products/Semiconductor/News/Flash/Flash_20040920_0000069917.htm (Sep 20,2004 / SEC) Samsung Introduces Industry's First 60-Nanometer 8-Gigabit NAND Flash Memory << OLE Object: Picture (Metafile) >> Korea – September 20, 2004: Samsung Electronics Co., Ltd., the leader in advanced semiconductor technology, announced today that it has developed the industry's first 60-nanometer (nm) 8-Gigabit (Gb) NAND Flash memory device for data storage medium such as low density mobile hard disks for mobile appliances. "NAND flash technology development continues to double density growth on an average of every 12 months," said Dr. Chang Gyu Hwang, president and CEO of Samsung Electronics' Semiconductor business. Verifying the New Memory Growth Model he first presented at the ISSCC's 2001 conference, Dr. Hwang said the industry has seen densities grow from 256 Megabit (Mb) in 1999, to 512Mb in 2000, 1Gb in 2001, 2Gb in 2002, 4Gb in 2003 and now 8Gb in 2004" [INTRODUCTION? Volume Production 1-2yrs later?]Samsung's advanced 60nm process technology is two thousandths the width of a piece of human hair, and achieves approximately 30 percent reduction in cell size over the 70nm 4Gb NAND Flash memory developed last year. The result is the world's smallest 0.0082µm2 [MLC? => 0.0164um2 SLC?] per bit cell size.The key to development at such high densities and fine circuitry design is a 3-D cell transistor structure and high-dielectric gate insulating technology that minimizes the interference level between cells. In addition, by utilizing the most widely used KrF lithography technology bit cost is reduced by 50 percent. Samsung is further enhancing its technology base by introducing its new multi level cell (MLC) technology in the 60nm process technology. The new 8Gb MLC NAND flash memory broadens the company's flash memory portfolio, meeting increasing market demand for efficient and cost effective non volatile storage devices. MLC technology also offers designers a competitive choice for low power, small form factor storage solutions that enable low density mobile internal hard disks (HDD) for compact mobile applications.The 8Gb NAND flash memory will allow designs of up to 16Gigabytes (GB) of storage on a single memory card. That 16GBs of memory translates into storage of up to 16 hours of DVD quality video or 4,000 (five minutes per song) MP3 audio files.According to market research firm iSuppli, the NAND flash market has doubled annually in volume from $900 million in 2001 to $4.2 billion in 2003. iSuppli expects NAND sales to reach $7.2 billion this year and $9.9 billion in 2005. This contrasts the growth of NOR flash sales, which shows a three percent CAGR and sales expanding from $6.7 billion in 2001 to a forecasted $7.6 billion in 2005. In line with these market trends, Samsung's NAND flash business has shown strong growth expanding from $400 million in 2001 to $2.1 billion in 2003. The company is focused on accelerating production of advanced devices with 2Gb NAND flash production shipping over 10 million pieces per month to date in 2004. Samsung expects to launch mass production of the 4Gb NAND flash by the first quarter of 2005. This year Samsung expects to double volume of NAND sales and account for 65 percent global market share.About Samsung Electronics:Samsung Electronics Co. Ltd. is a global leader in semiconductor, telecommunication, digital media and digital convergence technologies with 2003 parent company sales of US$36.4 billion and net income of US$5.0 billion. Employing approximately 88,000 people in 89 offices in 46 countries, the company consists of six main business units: Corporate Technology Operations, Digital Appliance Business, Digital Media Business, LCD Business, Semiconductor Business and Telecommunication Network Business. Recognized as one of the fastest growing global brands, Samsung Electronics is the world’s largest producer of color monitors, color TVs, memory chips, TFT-LCDs and VCRs. For more information, visit www.samsung.com . Work in Progress – Do Not Publish

    28. Samsung to mass produce 8Gbit NAND flash in 4Q 2005Hans Wu, Taipei; Jack Lu, DigiTimes.com [Thursday 14 October 2004] Samsung Electronics plans to begin mass production of its multi-level cell (MLC) 8Gbit NANDflash memory in the fourth quarter of next year, according to Kim Il-ung, vice president of Samsung’s memory product group, during an October 12 conference in Taiwan. In September, Samsung announced the 8Gbit chip, designed with 60nm process technology. The company said in a press release that the chip will allow designs of up to 16GB of storage on a single memory card. Samsung expects to launch a 16Gbit MLC NAND flash memory chip in 2007, Kim added. Although worldwide supply may start outpacing demand in the second quarter of next year, Samsung plans to raise wafer-starts for NAND flash to 45,000 12-inch wafers per month, up from 35,000 wafers this quarter, Kim indicated. Samsung had wafer starts of 45,000 12-inch wafers per month in the second quarter, the company said in a June web cast for its second-quarter results. Its first 12-inch fab, Fab 12 ran at a full capacity of 40,000 wafers per month and the new Fab 13 at 5,000 wafers per month. According to local company sources, Samsung forecasts worldwide NAND flash supply will lag demand by 0.9% next quarter but will then outpace demand over the following two quarters as more makers begin shipping. Supply is expected to again trail demand in the fourth quarter of 2005, the sources said. In related news, Kim said Samsung may allocate about US$5 billion for capital expenditure next year, compared to US$4.1 billion this year. Samsung NAND Flash Supply-and-Demand Forecast for 2005 Q1 Q2 Q3 Q4 Surplus (Shortage) (0.9%) 4.7% 1.6% (2.1%) Source: company, compiled by DigiTimes, October 2004. Work in Progress – Do Not Publish

    29. http://www.semiconductor.com/resources/newsletters/088_flash_mailer.asphttp://www.semiconductor.com/resources/newsletters/088_flash_mailer.asp “…One of the flash highlights of the past few months was the arrival of the premier 90nm flash offering from Samsung, K9W8G08U1M-YCB0. With its die size of 144mm² for a 2G device, it is the density leader of the current industry. SI also investigated several Multi Level Cell (MLC) devices during the season, including the Toshiba 2 G 130nm MLC NAND Flash TC58DVG14B1FT10, with a die size of 149 mm². This should be of interest to all Single Bit per Cell (SBC) clients, as the Mb/mm² density of the Toshiba device approaches that of the 90nm technology, while utilizing the more mature and less expensive 130nm process node…” “…Hynix 512M NAND Flash, Double unit density of other 512Mb NAND vendors with 6.25 Mb/mm2[81.9mm2/512Mb array area? = 0.153u2/cell? vs. 0.08u2 “90nm” ST citation]. Identical die markings to ST Microelectronics 512Mb NAND flash...” “…Samsung 8G (4 X 2G) 90nm NAND FlashInsight Award Winner - Most Innovative Non-Volatile MemorySamsung's 90 nm NAND process is at the forefront of flash technology Work in Progress – Do Not Publish