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a brief introduction of integrated circuits

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a brief introduction of integrated circuits

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  1. a brief introduction of integrated circuits RuomeiBian 2018.07.16

  2. Contents • Overview and history • Development • Manufacturing • Attempt

  3. Overview and history

  4. An integrated circuit or monolithic integrated circuit (also referred to as an IC, a chip, or a microchip) is a set of electronic circuits on one small flat piece (or "chip") of semiconductor material, normally silicon. 

  5. Vacuum tubes invented in 1904 by Fleming Large, expensive, power-hungry, unreliable • Invention of the bipolar transistor (BJT) 1947 Shockley, Bardeen, Brattain – Bell Labs

  6. The idea of the integrated circuit was conceived by Geoffrey Dummerin 1952. • Jack Kilby was working at Texas Instruments at the time, where he had an idea to construct all of the parts of an electronic circuit on a single chip. He soon put his idea into reality, and built the world’s first integrated circuit on September 12, 1958, on a slab of germanium. • Half a year after Kilby, Robert Noyce at Fairchild Semiconductor developed a new variety of integrated circuit, more practical than Kilby‘s implementation. Which was made of silicon.

  7. 2300 transistors 108 KHz operation PMOS only (10 um process) • Fairchild Semiconductor was home of the first silicon-gate IC technology with self-aligned gates, the basis of all modern CMOS computer chips. The technology was developed by Italian physicist Federico Fagginin 1968. In 1970, he joined Intel in order to develop the first single-chip central processing unit(CPU) microprocessor, the Intel 4004, for which he received the National Medal of Technology and Innovation in 2010. The 4004 was designed by Busicom's Masatoshi Shima and Intel's Ted Hoff in 1969, but it was Faggin's improved design in 1970 that made it a reality.

  8. Classification • Digital ICs  logic ICs, memory chips, interface ICs (level shifters, serializer/deserialier, ect. ) power management ICs, and programmable devices • Analog ICs linear ICs and RF ICs. • Mixed-signal ICs data acquisition ICs (including A/D converters, D/A converter, digital potentiometers) and clock/timing ICs.

  9. Generations Also WSI(Wafer-scale integration), SOC(system-on-a-chip) and 3D-IC(three-dimensional integrated circuit) 

  10. ICs and IC families • The 555 timer IC • The 741 operational amplifier • 7400 series TTL logic building blocks • 4000 series, the CMOS counterpart to the 7400 series (see also: 74HC00 series) • Intel 4004, the world's first microprocessor, which led to the famous 8080 CPU and then the IBM PC's 8088, 80286, 486 etc. • The MOS Technology 6502 and Zilog Z80 microprocessors, used in many home computers of the early 1980s • The Motorola 6800 series of computer-related chips, leading to the 68000 and 88000 series (used in some Apple computers and in the 1980s Commodore Amiga series) • The LM-series of analog integrated circuits

  11. Development

  12. Major enabling factors • 1950s——integrated circuit(IC)——by Jack Kilby and Robert Noyce • 1963——complementary metal-oxide-semiconductor (CMOS) ——by Frank wanlass • 1967——dynamic random-access memory (DRAM) technology ——by  Robert Dennard at IBM (1980s ——flash memory ——Fujio Masuoka at Toshiba) • 1980—— chemically-amplified photoresist ——by Hiroshi Ito, C. Grant Willson and J. M. J. Fréchet at IBM • 1980——deep UV excimer laser photolithography ——by Kanti Jain[57] at IBM (1970s——excimer lasers lithography—— by Nikolai Basov, V. A. Danilychev and Yu. M. Popov at the Lebedev Physical Institute)

  13. Moore‘s law is an observation and projection of a historical trend and not a physical or natural law. • Intel stated in 2015 that the pace of advancement has slowed, starting at the 22 nm feature width around 2012 • Moore's second law(Rock's law): The capital cost of a semiconductor fab also increases exponentially over time. • One of the key challenges of engineering future nanoscale transistors is the design of gates. As device dimension shrinks, controlling the current flow in the thin channel becomes more difficult.

  14. Recent years Each generation of the semiconductor manufacturing process——technology node Which is designated by the process' minimum feature size

  15. FinFET • 2000 • University of California, Berkeley • Profs. Chenming Hu, Tsu-Jae King-Liu and Jeffrey Bokor


  17. The Lilienfield transistor As or BF2 for device As or B for Gate NATURE NANOTECHNOLOGY DOI: 10.1038/NNANO.2010.15

  18. Nanoscale, 2013, 5, 2437–2441 | 2437

  19. single-electron devices may find use as ultradense non-volatile memories, nanoscale hybrid piezoelectric and charge sensors, as well as building blocks in quantum information processing and simulation platforms sketch-based single-electron transistor (SketchSET) at the three-unit-cell LaAlO3/SrTiO3 interface NATURE NANOTECHNOLOGY DOI: 10.1038/NNANO.2012.21 NATURE NANOTECHNOLOGY DOI: 10.1038/NNANO.2011.56

  20. Manufacturing Fabrication andPackaging

  21. Making Wafers

  22. Deposition: hysical vapor depositionp (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition(ALD) among others. • Removal: Etch processes (either wet or dry) and chemical-mechanical planarization (CMP). • Patterning: lithography. Extreme ultraviolet radiation (EUV) • Modification of electrical properties : doping transistor sources and drains, Then annealing to activate the implanted dopants. Other way : UV processing (UVP). Processing

  23. Processing Front-end-of-line (FEOL) processing Gate oxide and implants Back-end-of-line (BEOL) processing (Metal layers and Interconnect)

  24. Test and packaging • Test • Yield(maybe less the30%) • Wafer Final Test (WFT) • Electronic Die Sort (EDS) • Circuit Probe (CP) • Packaging • plastic (thermoset or thermoplastic) or ceramic • Design • Materials • Type • Through-hole package • Surface mount • Chip carrier • Pin grid array • Flat package • Small outline package • Chip-scale package • Ball grid array • Transistor, diode, small pin count IC packages • Multi-chip packages(3D)

  25.  3D packaging:Through-silicon vias (TSVs) ——the National Changhua University of Education in Taiwan

  26. attempt

  27. Classification of circuit technologies Intel 2017? 7nm For high speed For RF

  28. TFET APPLIED PHYSICS LETTERS 98, 093501 (2011)

  29. several attempts

  30. Thank you

  31. backup