1 / 7

HW5: Mentor Graphics I “ Design of a CMOS Inverter”

HW5: Mentor Graphics I “ Design of a CMOS Inverter”. Osamah Rawashdeh EE584 Fall 02. Overview. Schematic Capture (Design Architect TM ) Functional Simulation (Quicksim II TM ) Layout (IC Station TM ) Analog Simulation (Accusim II TM ). Schematic in Design Architect TM.

lore
Download Presentation

HW5: Mentor Graphics I “ Design of a CMOS Inverter”

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. HW5: Mentor Graphics I“ Design of a CMOS Inverter” Osamah Rawashdeh EE584 Fall 02

  2. Overview • Schematic Capture (Design ArchitectTM) • Functional Simulation (Quicksim IITM) • Layout (IC StationTM) • Analog Simulation (Accusim IITM)

  3. Schematic in Design ArchitectTM • Transistor-level schematic capture • Symbol creation • Viewpoint creation

  4. Logic Simulation in Quicksim IITM Only functional correctness is examined

  5. Inverter Layout in IC StationTM • Channel length = 2 λ • Channel width • n-MOS = 5 λ • p-MOS = 10 λ • Metal rail width = 5 λ • Contacts = 2 λ x 2 λ • Cell pitch = 50 λ • Cell origin set • Inverter layout conforms to DRC and LVS rules

  6. Analog Simulation in Accusim IITM • Simulation is based on parameters extracted from physical layout

  7. Measurements in Accusim IITM Design and verification of a CMOS inverter concluded.

More Related