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Advantages of Using CMOS

Advantages of Using CMOS

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Advantages of Using CMOS

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  1. Advantages of Using CMOS • Compact (shared diffusion regions) • Very low static power dissipation • High noise margin (nearly ideal inverter voltage transfer characteristic) • Very well modeled and characterized • Mechanically robust • Lends itself very well to high integration levels • “Analog” CMOS process usually includes non-salicided poly layer for linear resistors. • SiGe BiCMOS is very useful but is a generation behind currently available standard CMOS Prof. M. Green / U.C. Irvine

  2. Transistor fT Calculation VDD fT is the frequency at which becomes 1. id ig vgs Cgs VGS fT gives a fundamental speed measure of a technology. 0.25 µm CMOS: fT~ 23GHz (VDD= 2.5V) 0.18 µmCMOS: fT ~ 57GHz (VDD = 1.8V) Prof. M. Green / U.C. Irvine

  3. Assume: Wp = 3Wnfor optimum noise margin. Lp = Ln = Lmin Operation is 4X slower than theoretical maximum due to n-channel & p-channel gates connected in parallel. Static CMOS propagation delay: Vout Vin (Actual  values will be higher due to high diffusion capacitances present in sub-micron transistors.) Prof. M. Green / U.C. Irvine

  4. Verifying with simulation: n-channel ac simulation to determine fT: CMOS inverter transient simulation: IG Vout Vin ID fT = 57GHz Prof. M. Green / U.C. Irvine

  5. Vin Vout ISS IDD Single-Ended Signaling in CMOS VDD IDD Vin Vout sub ISS VSS Series R & L cause supply/ground bounce. Resulting modulation of transistor Vt’s result in pattern-dependent jitter. Prof. M. Green / U.C. Irvine

  6. Effect of Supply/Ground Bounce on Jitter data in data out clock in clock out Rs = 5Ls= 5nH clock out Rs = 0 Ls= 0 clock out Rs = 5 Ls= 5nH data out Prof. M. Green / U.C. Irvine

  7. Advantages of static CMOS gates: • Simple & straightforward design. • Robust operation. • Nearly zero static power dissipation. Disdvantages of static CMOS gates: • Full speed of transistors not exploited due to n-channel & p-channel gate in parallel at load. • Single-ended operation causes current spikes leading to VDD/VSS bounce. • Single-ended operation also highly sensitive to VDD/VSS bounce leading to jitter. Summary of CMOS Gate Performance Prof. M. Green / U.C. Irvine

  8. VDD R R Vout+ Vout- CL CL Vin+ Vin- ISS Current-Mode Logic (CML) CML inverter: • Based on conventional differential pair • Differential operation • Inherent common-mode rejection • Very robust in the presence of common- • mode disturbances (e.g., VDD / VSS bounce) Prof. M. Green / U.C. Irvine

  9. To keep current source transistor in saturation: DC Biasing of CML Inverter VDD + + R R _ _ VS + + _ _ VGS VGS ISS VBIAS Prof. M. Green / U.C. Irvine

  10. Logic Swing & Gain of CML Inverter To achieve full current switching: for correct operation VDD R R VDD-ISSR VDD ISS 0 CL CL VDD VDD-ISSR ISS Prof. M. Green / U.C. Irvine

  11. Small-Signal Behavior of CML Inverter Small-signal voltage gain: rise/fall time constant: (Assuming fanout of 1) Recall for full switching Note: rising & falling time constants are the same Prof. M. Green / U.C. Irvine

  12. Speed vs. Gain in Logic Circuits fast input transition: step response determined by  slow input transition: step response determined by Av Largest possiblegain-bandwidth productis desirable. Prof. M. Green / U.C. Irvine

  13. Relationship between Av,  , and Vswing “large-signal” gain-bandwidth product Larger logic swing preferred for higher gain-bandwidth product Larger Vswing Larger Vmin smaller W/L larger current density Prof. M. Green / U.C. Irvine

  14. Thought Experiment Slower! R R R R ISS ISS Suppose we decrease current density by increasing W/L: Prof. M. Green / U.C. Irvine

  15. Note that the load is only one gate capacitance: CML speed ~ 2.5 times faster than static CMOS n-channel ac simulation to determine fT: CML buffer transient simulation: IG ID fT = 57GHz Prof. M. Green / U.C. Irvine

  16. Once Vswing has been chosen, designer can trade off between gain & bandwidth by parameterizing between R & ISS: Higher speed: ISSR Higher gain: ISSR • Typical Vswing: • Should be large enough to allow sufficient gain-bandwidth product. • Should be small enough to prevent transistors from going into triode. • * CML will still work in triode (unlike BJT), but there is no additional • speed benefit. Prof. M. Green / U.C. Irvine

  17. ISS ISS Other Benefits of CML Gates • Constant current bias VDD / VSS bounce greatly reduced KCL sets this current to be nearly constant. Prof. M. Green / U.C. Irvine

  18. data in data out clock in clock out Rs = 5Ls= 5nH clock out Rs = 0 Ls= 0 clock out Rs = 5 Ls= 5nH data out Prof. M. Green / U.C. Irvine

  19. CML: buffer inverter • Non-inverting buffer available without additional delay: CMOS: tp 2tp buffer inverter Prof. M. Green / U.C. Irvine

  20. Fanout & Scaling of CML Gates R R Vout- Vout+ 1x = Vin+ Vin- ISS R/n R/n Vout- Vout+ nx All voltages unchanged from unit-sized buffer. Currents & power increase by factor of n. = Vin+ Vin- nISS Prof. M. Green / U.C. Irvine

  21. For fanout of n: increases linearly with fanout. Prof. M. Green / U.C. Irvine

  22. to minimize Should set degradation due to interconnect capacitance From interconnect, etc.; assumed not to scale with buffer sizes Power (proportional to n) determined primarily by interconnect capacitance! Prof. M. Green / U.C. Irvine

  23. + VGS _ CML buffer design procedure: • Determine largest allowable ISS (usually limited by electromigration constraints) • Choose “unit-sized” n-channel transistor (typically W/L=20) • Run a series of simulations to determine optimum value of R: • R too small: full current switching not achieved • R too large: slower than necessary • Choose minimum scaling factor after laying out some test buffers of various sizes and determining approximate value of interconnect capacitance Cp. Sub-micron MOSFETs obey square-law characteristics only in a limited region! Mobility reduction (linear) Square-law behavior Weak inversion (exponential) VGS Prof. M. Green / U.C. Irvine

  24. 1. Determine largest allowable ISS standard layout shared drain (1/2 diffusion capacitance) Imax independent of W determined by electromigration limits Prof. M. Green / U.C. Irvine

  25. CML Design Procedure Example R = 900 ISSR = 360mV tp = 10ps R too small Choose: R = 1200 ISSR = 480mV tp = 12ps *R optimum* R = 1500 ISSR = 600mV tp = 14ps R too large Prof. M. Green / U.C. Irvine

  26. Parameterizing Between Gain & Bandwidth ISS = 100 µA R = 4.8 k Av= 9.3 dB BW = 2.6 GHz ISS = 200 µA R = 2.4 k Av= 7.1 dB BW = 5.5 GHz ISS = 400 µA R = 1.2 k Av= 3.9 dB BW = 11.5 GHz Prof. M. Green / U.C. Irvine

  27. Parameterized CML Buffer GSCALE: Global scaling parameter (depends on Cp) MSCALE: Local scaling parameter (depends on fanout or bit rate) GBW: Gain-bandwidth parameter Prof. M. Green / U.C. Irvine

  28. CML with p-channel Active Load Can be used if linear resistors are not available. p-channel load transistors operates in triode region: Increased capacitance and mismatch result Prof. M. Green / U.C. Irvine

  29. Capacitance Comparison (1) gate channel sub Poly resistor: p-channel MOSFET: Prof. M. Green / U.C. Irvine

  30. Capacitance Comparison (2) (Numbers based on TSMC 180nm CMOS process) Cpoly-sub  Cchannel-sub : 0.13 fF/m2 Cdepletion : 1.20 fF/m2 Cchannel-gate : 7.80 fF/m2 Poly resistor: Wpoly= 0.6 Lpoly = 2.5 = 0.1 fF Wchannel= Wdiff= 2.5 µm Lchannel = 0.18 µm Ldiff = 0.3 µm p-channel MOSFET: = 0.9 fF + 1.8 fF + .03 fF = 2.8 fF Prof. M. Green / U.C. Irvine

  31. Capacitance Comparison (3) R = 1.2 k s = 235  Wr = 0.6 µm Lr = 2.5 µm Cres = 0.1 fF Wp = 2.5 µm Ldiff = 0.3 µm Cd2 = 2.8 fF M2 M2 M1 M1 M1 M1 Cd1 = 3.7 fF Cg1 = 5.8 fF Prof. M. Green / U.C. Irvine

  32. Pulse Response ComparisonPWin = 100ps p-channel load (W/L)p = 2.5 µm / 0.18 µm td = 20 ps; PWout = 98 ps resistor load R = 1.2 k td = 16 ps; PWout = 100 ps Prof. M. Green / U.C. Irvine

  33. Eye Diagram Comparisonincluding mismatch effects resistor load = 1.5% mismatch p-channel load = 4% mismatch 160mV gate-referred mismatch DCD ISI Prof. M. Green / U.C. Irvine

  34. MA MA MA MA MB MB Series-Gated CML Topology XOR gate: Common-mode voltage of BP/N critical: • Too low  current source transistor biased in triode • Too high  Transistors MB biased in triode Prof. M. Green / U.C. Irvine

  35. Series-Gated CML (2) VS I1 I2 BP BN ISS Transistors should be biased in saturation to realize maximum gm . Especially important when gate voltages exhibit slow slew rates Slope = gm -ISS Prof. M. Green / U.C. Irvine

  36. VB(cm) = 1.3 VB(cm) = 1.0 VB(cm) = 1.6 DC current: VB(cm) = 1.3 VB(cm) = 1.0 Transient response: (400mV amplitude sine wave applied to BP/BN) VB(cm) = 1.6 t Prof. M. Green / U.C. Irvine

  37. Level-Shifting CML Buffer Used to drive clock inputs of series-gated CML gates VDD Output levels: + Rcm _ R R ISS • DC levels shifted down by ISSRcm • Vswing unchanged Prof. M. Green / U.C. Irvine

  38. CML Select Circuit R R OUTP OUTN AP AN BP BN SELA SELB ISS Be reassigning the inputs, the XOR can be transformed into a Select circuit. Used in a 2:1 multiplexer. SELA AP/N BP/N OUTP/N Prof. M. Green / U.C. Irvine

  39. OUTP OUTN DP DN CKP CKN ISS CML Latch By setting BP/N = OUTP/N, we can construct a CML latch: Prof. M. Green / U.C. Irvine

  40. CML D Flip-Flop XP OUTP XN OUTN DP DN XP XN CKP CKN CKN CKP CKP/N DP/N OUTP/N Output OUTP/N is synchronized with CKP/N falling edge. Prof. M. Green / U.C. Irvine

  41. R R dc operating points VGG IGG CML Latch Design Considerations IGG slope=1/rgg VGG Necessary criterion for bistability: at middle operating point (Equivalent to loop gain = gmR > 1) Prof. M. Green / U.C. Irvine

  42. Avoiding Latch Transparency XP/N “transparent” latch Prof. M. Green / U.C. Irvine

  43. XP XN XP XN GBW parameter can be increased to ensure bistability. R=1000 R=800 R=600 Prof. M. Green / U.C. Irvine

  44. Buffering Clock Signals (1) Clock signals (generated from VCO or clock divider) often drive large capacitive loads. 1x 1x C … n 1x C C Fanout = n For a large fanout, attenuation of clock amplitude will occur. Prof. M. Green / U.C. Irvine

  45. Buffering Clock Signals (2) ktp n x k2 x … k x 1x m stages less attenuation at each stage Now  is increased by k << n Delay = mktp Power = P1(1 + k + k2 + … + n) Power dissipated by first stage As fclock 1/tp then k  1; number of stages and total power become very large. Prof. M. Green / U.C. Irvine

  46. Buffering Clock Signals (3) Since clock signal is made up of a single frequency (+ harmonics), resonance can be used to increase gain with greatly reduced power dissipation. Resonant frequency: at resonance If lossless inductors were available, we could achieve high gain at any frequency simply by choosing the correct inductor value. Prof. M. Green / U.C. Irvine

  47. l pH/m l l On-Chip Passive Elements l l Resistor: t w l Capacitor: l (+ fringing) w d substrate l Inductor: t w Inductance calculation much more complicated! Prof. M. Green / U.C. Irvine

  48. l pH/m l l l t w Special case of Greenhouse result Note for l>> w, L is a weak function of w To increase effective inductance per unit length, we make use of mutual inductance via spiral structure: Prof. M. Green / U.C. Irvine

  49. Modeling of Spiral Inductor 1 2 • Accurate lumped model should include: • Series inductance (self + mutual) & resistance • Skin effect (frequency dependent series resistance) • Interwinding capacitance • Capacitance to substrate • Substrate capacitance & loss number of turns n = 2 • Procedure for constructing lumped model: • 2-port s-parameters over frequency range of interest • (this comes from the inductor simulator) • Choose lumped circuit topology. • Run simulations to find the optimal lumped circuit • element values such that the the circuit s-parameters • are sufficiently close to the inductor’s s-parameters • (can use .net and .optimize in HSPICE) • Design of inductor requires: • inductor simulation package • (e.g., asitic) • trial and error • conversion to lumped element model Prof. M. Green / U.C. Irvine

  50. Modeling of Spiral Inductor (cont.) Link to “asitic” web pages: http://rfic.eecs.berkeley.edu/~niknejad/asitic.html Inductor magnitude impedance vs. frequency • Parameters most relevant to circuit designers: • Inductance • Series resistance • Self-resonant frequency Prof. M. Green / U.C. Irvine