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Micron Engineering Clinic

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  1. Welcome to Micron Engineering Clinic Analysis and Optimization of Multi Gb/s Chip-to-Chip Communication Micron Engineering Clinic Fall ‘08 – Spring ‘09

  2. Team Members Documentation Lead Raheem Alhamdani - CE Technical Leads Bryson Kent - EE Jordan Kemp - EE Lucas Loero - EE Team Lead Ben Meakin – CE Micron Engineering Clinic Fall ‘08 – Spring ‘09

  3. Introduction and Motivation for Modeling and Verification of Interconnects Raheem Alhamdani Documentation Lead Computer Engineer Alhamdan@eng.utah.edu Micron Engineering Clinic Fall ‘08 – Spring ‘09

  4. Introduction The Sponsor: • Manufacturer of DRAM, Flash Memory, and Image Sensor Integrated Circuits What Have They Asked Us To Do? • Design a software application for modeling and verification of chip-to-chip interconnects Micron Engineering Clinic Fall ‘08 – Spring ‘09

  5. Introduction What is Verification? • Proving through tests and formal methods that a design does what it is intended to do What are Chip-to-Chip Interconnects? • Electrical systems for communication between two integrated circuits hardwaresecrets.com Micron Engineering Clinic Fall ‘08 – Spring ‘09

  6. Motivation Background Memory and I/O Devices Operate Much Slower than CPU Access to Off-Chip Resources is Expensive ~ 300 cycles - Usually Cycles are Wasted Demand for Low-Power yet High-Performance - Can’t Have Wasted Cycles! Goal: Speed Up Devices and Speed Up Interconnect Micron Engineering Clinic Fall ‘08 – Spring ‘09

  7. Problem As Devices Move Towards Being Smaller, Faster, Lower Power Interconnects Become Slower, Noisier, and Unreliable Issues: • Inter-Symbol Interference (ISI) • Co-Channel Interference • Timing Jitter • Voltage Noise Conventional Testing Methodologies are not Feasible or Sufficient Micron Engineering Clinic Fall ‘08 – Spring ‘09

  8. Eye Diagram • What is an eye diagram? A useful tool for the qualitative analysis of signal used in digital transmission. Voltage Time Micron Engineering Clinic Fall ‘08 – Spring ‘09

  9. Eye Diagram How is it created? Voltage Time Voltage Time Bits Superimposed 1 Unit Interval (UI)‏ Micron Engineering Clinic Fall ‘08 – Spring ‘09

  10. Eye Diagram (Noise) What Causes Noise? • Interference from neighboring wires (Co-Channel Interference)‏ • Electromagnetic Interference • Link resistance, capacitance, and inductance Bit-stream Voltage Voltage Noise Time Voltage Time Bits Superimposed 1 Unit Interval (UI)‏ Micron Engineering Clinic Fall ‘08 – Spring ‘09

  11. Eye Diagram (Jitter) What Causes Jitter? • Clock Variation (Skew)‏ • Reflection • General Timing Uncertainty Bit-stream Voltage Time Jitter Voltage Time Bits Superimposed 1 Unit Interval (UI)‏ Micron Engineering Clinic Fall ‘08 – Spring ‘09

  12. Real Eye Diagram How to interpret it? Data Jitter Clock Jitter Signal Noise Vref Noise + ReceiverSensitivity Vref Data Signal Clock Signal Micron Engineering Clinic Fall ‘08 – Spring ‘09

  13. Solution Our Objective is Not to Solve These Problems Through Better Design, but to Provide Designers with a Tool That Correctly Models and Verifies Interconnects With These Problems Deliverables: • Cross Platform App with Graphical User Interface • Provide Worst-Case and Statistical Based Link Analysis • Spice Compatible • Correctly Model Co-Channel Interference and Tx/Rx Jitter Micron Engineering Clinic Fall ‘08 – Spring ‘09

  14. My Roles • Project Documentation Meeting minutes, Time-line, Progress Report , Presentations, Proposal and links are all on the team’s website: www.eng.utah.edu/~alhamdan/Micron/Micron.html • Graphical User Interface and Software Development GUI Software skeleton Plotting code Code documentation Micron Engineering Clinic Fall ‘08 – Spring ‘09

  15. Team’s website Micron Engineering Clinic Fall ‘08 – Spring ‘09

  16. Meeting Minutes Micron Engineering Clinic Fall ‘08 – Spring ‘09

  17. Bibliography B. K. Casper, M. Haycock, and R. Mooney, “An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling scheme”, in Digest of Technical Papers from the IEEE Symposium on VLSI Circuits, June 2002, pp. 54–57. B. K. Casper , G. Balamurugan, J. E. Jaussi, J. Kennedy, M. Mansuri, “Future microprocessor interfaces: Analysis, design and optimization”, in Proceedings of the IEEE Custom Integrated Circuits Conference, Sept. 2007, pp. 479-486. P. K. Hanumolu, B. K. Casper, R. Mooney, G. Y. Wei, and U. K. Moon, “Jitter in high-speed serial and parallel links”, in Proceedings of the IEEE International Symposium on Circuits and Systems, May 2004, pp. 425–428. Pavan Kumar Hanumolu, Bryan Casper, Randy Mooney, Gu-Yeon Wei, and Un-Ku Moon, “Analysis of PLL Clock Jitter in High-Speed Serial Links”, in IEEE Transactions on Circuits and Systems, November 2003, pp.879-886 Micron Engineering Clinic Fall ‘08 – Spring ‘09

  18. Questions? Micron Engineering Clinic Fall ‘08 – Spring ‘09

  19. Worst Case Verification of High Speed Interconnects Bryson Kent Technical Lead Electrical Engineer Bryson.kent@gmail.com Micron Engineering Clinic Fall ‘08 – Spring ‘09

  20. Introduction What is Worst Case analysis Why is the Worst Case important How to calculate the Worst Case What are the results Conclusion and implementation Micron Engineering Clinic Fall ‘08 – Spring ‘09

  21. Worst Case Analysis Summation of all negative effects Good representation of what can happen if certain conditions arise Verification of error free transmission Classic analysis of 1 trillion bits (1*10^12 bits) * (10^-6sec) = over 10 days Micron Engineering Clinic Fall ‘08 – Spring ‘09

  22. Worst Case Eye Diagram Voltage Vs one period of time Distortion sources add to close the eye From the eye diagram we can calculate a system pass fail WC1WC2 WC3 Pass/Fail Tim Hollis, Micron Senior Project Proposal Micron Engineering Clinic Fall ‘08 – Spring ‘09

  23. Inter-Symbol Interference Inter-Symbol interference is the main source of interference Data dependent jitter and Co-channel interference add to signal degradation Tim Hollis, Micron Senior Project Proposal Micron Engineering Clinic Fall ‘08 – Spring ‘09

  24. C(t) = transmitter symbol response P(t) = impulse response of the channel Worst-Case Computation • Worst case eye diagram due to Inter-symbol interference • Worst case eye diagram due to Inter-symbol interference and cochannel interference J. G. Proakis, “Digital Communication”, McGraw-Hill, 3rd Ed., 1995. B. K. Casper, M. Haycock, and R. Mooney, “An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes”, in Digest of Technical Papers from the IEEE Symposium on VLSI Circuits, June 2002, pp. 54–57. Micron Engineering Clinic Fall ‘08 – Spring ‘09

  25. Calculating the eye diagram Tim Hollis, Micron Senior Project Proposal Micron Engineering Clinic Fall ‘08 – Spring ‘09

  26. Results Calculated performance Vs given performance Micron Engineering Clinic Fall ‘08 – Spring ‘09

  27. Conclusion Worst case analysis is beneficial Computation is pulse based analysis User can define and add any distortion as desired Results of worst case analysis match results of given test case Micron Engineering Clinic Fall ‘08 – Spring ‘09

  28. Questions? Micron Engineering Clinic Fall ‘08 – Spring ‘09

  29. Statistical Analysis ofElectrical Signaling Jordan Kemp Technical Lead Electrical Engineering jordykemp@hotmail.com Micron Engineering Clinic Fall ‘08 – Spring ‘09

  30. Introduction • Why • What • How • Summary Micron Engineering Clinic Fall ‘08 – Spring ‘09

  31. Introduction • Worst Case Eye good for Pass/Fail Mask, but doesn’t give details Pass/Fail Mask • Need for probability of error, rather than rigid “Pass/Fail” Micron Engineering Clinic Fall ‘08 – Spring ‘09

  32. Introduction • Use channel impulse response, p(t), and transmitter symbol response, c(t)‏ • Find PDF (Probability Density Function) & CDF (Cumulative Distribution Function) of the channel output Micron Engineering Clinic Fall ‘08 – Spring ‘09

  33. Introduction • Plot BER eye-diagram as a function of sample time, sample voltage, and probability of error • Shows BER of transmitted data given timing uncertainty (data jitter, clock jitter) and voltage uncertainty (VREF, Rx sensitivity, ISI)‏ Micron Engineering Clinic Fall ‘08 – Spring ‘09

  34. Why • Certain number of errors per number of bits sent specified by user/system Bit Error Rate (BER) = • Usually specified below • Would require a 1 TRILLION bit simulation! • TrendsIncrease: Speed, Capacity Decrease: Form-Factor, Power, Cost All above decrease Signal Integrity • Theoretically impossible to send error-free data Micron Engineering Clinic Fall ‘08 – Spring ‘09

  35. What • Probabilistic data eye using channel impulse response, p(t), and transmitter symbol response, c(t) to find the PDF & CDF of the channel output • What is a PDF? - Probability Density Function - Shows the probability that a specific value is likely to happen - Integrates to 1 • What is a CDF? - Cumulative Distribution Function - Shows the probability is less than or equal to a specific value - Integral of the PDF Micron Engineering Clinic Fall ‘08 – Spring ‘09

  36. How (1) 1st Way (from *Casper paper): Recursively convolve 1UI sample terms assuming equal probability of a transmitted ‘0’ or ‘1’ 1UI y(t)‏ [0 -0.01]  [0 0.59]  [0 -0.07]  [0 0.015]  [0 0.055]  [0 0.2]  [0 0.5]  [0 0]  [0 0.7] 0.59 0.0 (Each step scaled by ½ to account for P(0) = P(1) ) Micron Engineering Clinic Fall ‘08 – Spring ‘09

  37. How (1) Problems: • VERY hardware intensive (must compute multiple convolutions)‏ • Must maintain certain amount of resolution, slowing computations down even more • Very quickly run out of memory performing calculations [0 -0.01]  [0 0.59]  [0 -0.07]  [0 0.015]  [0 0.055]  [0 0.2]  [0 0.5]  [0 0]  . . . . 1.452  1 (no decimal resolution)1.452  1.4 (one decimal resolution)1.452  1.45 (two decimal resolution)…… delta function @ 1: [0 1 0 …] 0 1 2 . . .delta function @ 1.4: [0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 …] 0 .1 .2 .3 .4 .5 .6 .7 .8 .9 1 1.1 1.2 1.3 1.4 1.5 . . . Micron Engineering Clinic Fall ‘08 – Spring ‘09

  38. How (2) Implemented Method (modified from previous): • Same points taken as before, but add instead of convolve • Keeps track of locations of delta functions • Keeps track of heights of each delta • Plot locations versus heights [0 -0.01] + [0 0.59] + [0 -0.07] + [0 0.015] + [0 0.055] + [0 0.2] + [0 0.5] + [0 0] + [0 0.7] Micron Engineering Clinic Fall ‘08 – Spring ‘09

  39. How (2) Height = 0.5 -.01 0 Height = 0.5 0 .59 Height = 0.25 -.01 0 .58 .59 • [0 -0.01]  [0 0.59] = [0 -.01 (0+.59) (-.01+.59)] = [-.01 0 .58 .59] • Instead of convolving, proposed method adds & concatenates Micron Engineering Clinic Fall ‘08 – Spring ‘09

  40. How (2) Advantages: • VERY quick • Easy to implement • Infinite precision (in theory)‏ Micron Engineering Clinic Fall ‘08 – Spring ‘09

  41. Summary • Use channel impulse response, p(t), and transmitter symbol response, c(t) • Find PDF (Probability Density Function) & CDF (Cumulative Distribution Function) of the channel • Plot BER eye-diagram as a function of sample time, sample voltage, and probability of error • Shows BER of transmitted data given timing uncertainty (data jitter, clock jitter) and voltage uncertainty (VREF, Rx sensitivity, ISI) Micron Engineering Clinic Fall ‘08 – Spring ‘09

  42. Questions? Micron Engineering Clinic Fall ‘08 – Spring ‘09

  43. MODELING JITTER IN CHIP-to-CHIP COMMUNICATION M. Lucas Loero Technical Lead Electrical Engineer Lucas.loero@utah.edu Micron Engineering Clinic Fall ‘08 – Spring ‘09

  44. PRESENTATION OBJECTIVES • Defining Jitter • Problems caused by Jitter • Modeling Jitter • Receiver Jitter • Transmitter Jitter • Total Jitter Micron Engineering Clinic Fall ‘08 – Spring ‘09

  45. DEFINING JITTER Edge location shifted Voltage Time Jitter Ideal edge location Micron Engineering Clinic Fall ‘08 – Spring ‘09 Ideal edge location

  46. PROBLEMS CAUSED BY JITTER • Power supply and environment noise causes Jitter. • Jitter can lead to: • Time uncertainty • Suboptimal sampling time • Reduce noise margin Micron Engineering Clinic Fall ‘08 – Spring ‘09

  47. PROBLEMS CAUSED BY JITTER Micron Engineering Clinic Fall ‘08 – Spring ‘09

  48. MODELING JITTER • Model the effects of Jitter in high-speed serial links • Serial links are used for high-speed chip-to-chip communications Micron Engineering Clinic Fall ‘08 – Spring ‘09

  49. MODELING JITTER Serial Links Transmitter generates a train of pulses Decision circuit Transmitter clock Sampler Micron Engineering Clinic Fall ‘08 – Spring ‘09

  50. MODELING JITTER • Traditional approach to modeling jitter • There is two main problems with this approached • First, simulation time • Second, difficulty simulating serial links Micron Engineering Clinic Fall ‘08 – Spring ‘09