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CHAPTER 4

CHAPTER 4. Introduction to Shift Register By : Pn Siti Nor Diana Ismail. Register. A register is a memory device that can be used to store more than one-bit information

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CHAPTER 4

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  1. CHAPTER 4 Introduction to Shift Register By : Pn Siti Nor Diana Ismail

  2. Register • A register is a memory device that can be used to store more than one-bit information • A register is usually realized as several flip-flops with common control signals that control the movement of data to and from the register.(shifting data 1s and 0s) • A register can consist of one or more FF is used to store and shift data. • A register in digital circuit with2 basic function : data storage and data movement

  3. Basic Shift Register Function • Shift Register consists of an arrangement of Flip-flop. • Important in applications involving storage and transfer data in digital system. • Has no specified sequence of states. • D flip-flop is used

  4. Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 1 1 1 LSI 0 1 1 1 LSI Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 RSI 0 1 1 1 RSI 0 1 1 Shift Registers • Multi-bit register that moves stored data bits left/right ( 1 bit position per clock cycle) • Shift Left is towards MSB • Shift Right (or Shift Up) is towards MSB

  5. The flip-flop as a storage element Still remember the truth table for D flip flop? D CLK/C Q Q’_________________ 1 ↑ 1 0 SET (stores a 1) 0 ↑ 0 1 RESET (stores a 0)

  6. The flip-flop as a storage element When a 1 is on D, Q becomes a 1 at triggering edge of CLK or remains a 1 if already in the SET state When a 0 is on D, Q becomes a 0 at triggering edge of CLK or remains a 0 if already in the RESET state

  7. Basic data movement in shift registers(Four bits are used for illustration. The bits move in the direction of the arrows.)

  8. Type of register • Serial In / Serial Out Shift Registers (SISO) • Serial In /Parallel Out Shift Registers (SIPO) • Parallel In / Serial Out Shift Registers (PISO) • Parallel In / Parallel Out Shift Registers (PIPO)

  9. SRG n SERIN D Q CLK > SI SO CLOCK D Q CLK    SEROUT D Q CLK i. Serial In, Serial Out Shift Register (SISO) For a n-bit SRG: Serial Out = Serial In delayed by n clock period 4-bit shift register example: serin: 1 0 1 1 0 0 1 1 1 0 serout: - - - - 1 0 1 1 0 0 clock:

  10. D FFs diagram (SISO)

  11. 4- bit (1010) being entered serially into Serial In, Serial Out Shift Register (SISO)

  12. FF0 FF1 FF2 FF3 Clear 0 0 0 0 1010 0 0 0 0 101 0 0 0 0 0 10 1 0 0 0 00 1 0 1 0 0 000 Clear 1 0 1 0 0000 Serial In, Serial Out Shift Register (SISO)

  13. Clk FF0 FF1 FF2 FF3 0 Clear 0 0 0 0 1 1011001110 0 0 0 0 2 101100111 0 0 0 0 3 10110011 1 0 0 0 4 1011001 1 1 0 0 5 101100 1 1 1 0 6 10110 0 1 1 1 0 7 1011 0 0 1 1 10 8 101 1 0 0 1 110 9 10 1 1 0 0 1110 10 1 0 1 1 0 01110 11 Clear 1 0 1 1 001110 Serial In, Serial Out Shift Register(SISO)

  14. Show state of 5-bit register for specified data input and clock waveform. Assume register initially clear all (0s)  SISO

  15. SRG n SERIN 1Q D Q CLK > SI 1Q CLOCK 2Q    2Q D Q CLK nQ    nQ D Q CLK ii. Serial In, Parallel Out Shift register(SIPO) (SO) Serial to Parallel Converter Example: 4-bit shift register serin: 1 0 1 1 0 0 1 1 1 0 1Q: - 1 0 1 1 0 0 1 1 1 2Q: - - 1 0 1 1 0 0 1 1 3Q: - - - 1 0 1 1 0 0 1 4Q: - - - - 1 0 1 1 0 0 clock:

  16. SERIN D Q CLK SERIN 1Q D Q CLK CLOCK CLOCK D Q CLK 2Q D Q CLK       SEROUT D Q CLK nQ D Q CLK Can u see the difference?

  17. Serial In, Parallel Out Shift register (SIPO) • Data bits entered serially (right-most bit first) • Difference from SISO is the way data bits are taken out of the register – in parallel. • Output of each stage is available

  18. Example :Show the states of 4-bit register (SRG 4) for the data input and clocks waveforms. The register initially contains all (1s). Assume the register initially contains all 1s ~ HIGH. The register have 0110 after 4 clock pulse…

  19. 4-bit parallel in/serial out shift register (PISO)(logic symbol)

  20. 4-bit parallel in/serial out shift register (PISO) When signal = 1, • SHIFT When signal = 0,  LOAD

  21. 4-bit parallel in/serial out shift register (PISO) When signal = 0, • LOAD G1 – G3 enabled

  22. 4-bit parallel in/serial out shift register (PISO) When signal = 1, • SHIFT G4 – G6 enabled

  23. Example : Show the data input waveform for 4-bit register with parallel input and clock shift/load waveform…4-bit parallel in/serial out shift register (PISO)

  24. Can you try and trace the output for each FF stage until you get Q3?

  25. Let’s try to trace this one first… 1 0 1 0 Assume that the signal has values 011011 for 6 respective clock cycle For the parallel data input Assume D0 = 1, D1 = 0, D2 = 1, D3 = 0

  26. Let’s try to trace this one first… 0 1 1 1 0 0 0 CLK 1, Signal = 0 G1 – G3 Will get value = 1 G4 – G6 Will get value = 0 Referring to the AND gate theory, All gates that receives “0” values at shift/load can be ignored.

  27. Let’s try to trace this one first… 1 1 1 1 0 1 0 Now, AND the shift/load value with Respective data that goes into G4, G5, G6

  28. Clk Shift/Load Active signal Q0 Q1 Q2 Q3 0 Clear Clear 0 0 0 0 1 0 LOAD 1 0 1 0 2 1 SHIFT 1 1 0 1 3 1 SHIFT 1 1 1 0 4 0 LOAD 1 0 1 0 5 1 SHIFT 1 1 0 1 6 1 SHIFT 1 1 1 0 How do you put it in table? For the parallel data input Assume D0 = 1, D1 = 0, D2 = 1, D3 = 0

  29. Can you try and trace the output for each FF stage until you get Q3?

  30. D Q CLK D Q CLK Parallel to Serial Converter Load/Shift=1 Di Qi Load/Shift=0 Qi Qi+1      D Q CLK Parallel In, Serial Out Shift Register (PISO) CLOCK LOAD/SHIFT SERIN 1Q S 1D L 2Q S 2D L  NQ S SEROUT ND L

  31. Parallel In, Parallel Out Shift Register (PIPO) • Immediately following simultaneous entry of all data bits, it appear on parallel output.

  32. D Q CLK D Q CLK      D Q CLK Parallel In, Parallel Out Shift Register (PIPO) CLOCK LOAD/SHIFT SERIN S 1Q 1D L S 2Q 2D L General Purpose: Makes any kind of (left) shift register  S NQ ND L

  33. Parallel In, Parallel Out Shift Register (PIPO)

  34. Bi-directional Shift Registers • Data can be shifted left/right • A parallel load maybe possible • 74HC194 is a bidirectional universal shift register • A bidirectional Shift Register ~ - one is which data can be shifted either left or right. - can be implement by using gate logics that enable transfer data bit from one stage to next stage (to right/left) depend on level of control lines.

  35. Shift Registers Counter • Shift register counter is basically a shift register with serial output connect back to serial input to produce sequences. • Have 2 types :- (i) Johnson Counter = complement of output of last FF is connected back to D input of 1st FF. (ii) Ring Counter = utilize one FF for each state in it sequence.

  36. Example : Five-bit Johnson counters

  37. Example : A 10-bit Ring Counter • Assume initial state : 0000000101

  38. Shift Register Applications • Bit Serial Operations • Bit serial operations can be performed quickly through device iteration • Iteration (a purely combinational approach) is expensive (in terms of # of transistors, chip area, power, etc). • A sequential approach allows the reuse of combinational functional units throughout the multi-cycle operation

  39. Time Delay • Time delay can be adjust up/down by changing the clock frequency • Time delay can be increased by cascading shift register • Time delay also can be decreased by taking output from lower stage

  40. Example: The shift register as a time-delay device

  41. Serial to parallel Conversion • Use to reduce number of wires in transmission line. • e.g.:eight bits can sent serially over one wire, but it takes 8 wires to send same data in parallel • In the operation of serial to parallel converter: • - consists of 11 bits(start bit=always 0 and always begin HIGH to LOW transition,8 bits(D7-D0)=data bit(1 parity bit, 2 stop bits) • HIGH to LOW transition set the control flip-flop,enable the clock

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