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ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2009 Datapath and Control (Chapter 4)

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  1. ELEC 5200-001/6200-001Computer Architecture and DesignFall 2009 Datapath and Control(Chapter 4) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu ELEC 5200-001/6200-001 Lecture 7

  2. Von Neumann Kitchen ALU Start Control My choice PC Registers Processor Program Data Input Memory Output ELEC 5200-001/6200-001 Lecture 7

  3. Where Does It All Begin? • In a register called program counter (PC). • PC contains the memory address of the next instruction to be executed. • In the beginning, PC contains the address of the memory location where the program begins. ELEC 5200-001/6200-001 Lecture 7

  4. Where is the Program? Processor Memory Program counter (register) Machine code of program Start address ELEC 5200-001/6200-001 Lecture 7

  5. How Does It Run? Start PC has memory address where program begins Fetch instruction word from memory address in PC and increment PC ← PC + 4 to point to next instruction Decode instruction Execute instruction Save result in register or memory No Program complete? Yes STOP ELEC 5200-001/6200-001 Lecture 7

  6. Datapath and Control • Datapath: Memory, registers, adders, ALU, and communication buses. Each step (fetch, decode, execute, save result) requires communication (data transfer) paths between memory, registers and ALU. • Control: Datapath for each step is set up by control signals that set up dataflow directions on communication buses and select ALU and memory functions. Control signals are generated by a control unit consisting of one or more finite-state machines. ELEC 5200-001/6200-001 Lecture 7

  7. Add Datapath for Instruction Fetch 4 Instruction Memory PC Instruction word to control unit and registers Address ELEC 5200-001/6200-001 Lecture 7

  8. Register File: A Datapath Component 5 32 Registers (reg. file) reg 1 32 Read registers reg 1 data 5 reg 2 Write register 5 32 reg 2 data Write data 32 RegWrite from control ELEC 5200-001/6200-001 Lecture 7

  9. Multi-Operation ALU Operation select from control Operation select ALU function 000 AND 001 OR 010 Add 110 Subtract 111 Set on less than 3 zero ALU result overflow zero = 1, when all bits of result are 0 ELEC 5200-001/6200-001 Lecture 7

  10. R-Type Instructions • Also known as arithmetic-logical instructions • add, sub, slt • Example: add $t0, $s1, $s2 • Machine instruction word 000000 10001 10010 01000 00000 100000 opcode$s1 $s2 $t0 function • Read two registers • Write one register • Opcode and function code go to control unit that generates RegWrite and ALU operation code. ELEC 5200-001/6200-001 Lecture 7

  11. Datapath for R-Type Instruction • 000000 10001 10010 01000 00000 100000opcode $s1 $s2 $t0 function (add) Operation select from control(add) 5 32 Registers (reg. file) 10001 $s1 Read register numbers 3 32 zero 5 $s2 10010 ALU result 32 overflow Write reg. number 5 $t0 01000 Write data 32 RegWrite from control activated ELEC 5200-001/6200-001 Lecture 7

  12. Load and Store Instructions • I-type instructions • lw $t0, 1200 ($t1) # incr. in bytes 100011 01001 01000 0000 0100 1011 0000 opcode $t1 $t0 1200 • sw $t0, 1200 ($t1) # incr. in bytes 101011 01001 01000 0000 0100 1011 0000 opcode $t1 $t0 1200 ELEC 5200-001/6200-001 Lecture 7

  13. Datapath for lw Instruction 100011 01001 01000 0000 0100 1011 0000 opcode $t1 $t0 1200 MemWrite Operation select from control (add) 32 Registers (reg. file) 5 01001 $t1 Read register numbers 3 Read data 32 zero 5 result ALU Addr. Data memory overflow Write reg. number 5 $t0 01000 Write data Write data 32 32 RegWrite from control activated Sign extend MemRead activated 0000 0100 1011 0000 16 mem. data to $t0 ELEC 5200-001/6200-001 Lecture 7

  14. Datapath for sw Instruction 101011 01001 01000 0000 0100 1011 0000 opcode $t1 $t0 1200 MemWrite activated Operation select from control (add) 32 Registers (reg. file) 5 01001 $t1 Read register numbers 3 Read data 32 zero 5 $t0 result 01000 ALU Addr. Data memory overflow Write reg. number 5 32 Write data Write data $t0data to mem. 32 32 Sign extend RegWrite from control MemRead 0000 0100 1011 0000 16 ELEC 5200-001/6200-001 Lecture 7

  15. Branch Instruction (I-Type) • beq $s1, $s2, 25 # if $s1 = $s2, advance PC through 25 instructions 16-bits 000100 10001 10010 0000 0000 0001 1001 opcode $s1 $s2 25 Note: Can branch within ± 215 words from the current instruction address in PC. ELEC 5200-001/6200-001 Lecture 7

  16. 3 ALU Add Datapath for beq Instruction 16-bits 000100 10001 10010 0000 0000 0001 1001 opcode $s1 $s2 25 Operation select from control (subtract) 32 Registers (reg. file) 5 10001 $s1 Read register numbers 32 5 $s2 To branch control logic 10010 zero result 5 32 Write reg. number overflow Write data PC+4 Branch target 32 RegWrite from control From instruction fetch datapath 32 Sign extend Shift left 2 16 0000 0000 0001 1001 32 32 32 ELEC 5200-001/6200-001 Lecture 7

  17. J-Type Instruction • j 2500 # jump to instruction 2,500 26-bits 0000100000 0000 0000 0010 0111 0001 00 opcode2,500 32-bit jump address 0000 0000 0000 0000 0010 0111 00010000 bits 28-31 from PC+4 ELEC 5200-001/6200-001 Lecture 7

  18. 0 mux 1 Add Datapath for Jump Instruction Branch Jump Branch addr. 32 4 1 mux 0 32 32 PC+4 4 Shift left 2 28 Instruction Memory 32 PC 26 opcode (bits 26-31) to control 32 6 Address 32 Instruction word to control and registers ELEC 5200-001/6200-001 Lecture 7

  19. Jump 0-25 Shift left2 0 mux 1 4 Add 1 mux 0 ALU Branch opcode MemtoReg CONTROL RegDst 26-31 21-25 zero MemWrite MemRead ALU Instr. mem. PC Reg. File Data mem. 1 mux 0 16-20 0 mux 1 1 mux 0 11-15 Combined Datapaths ALU Cont. Sign ext. Shift left 2 0-15 0-5 ELEC 5200-001/6200-001 Lecture 7

  20. Control RegDst Jump Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite Instruction bits 26-31 opcode Control Logic 2 Instruction bits 0-5 funct. ALUControl to ALU ELEC 5200-001/6200-001 Lecture 7

  21. Control Logic: Truth Table ELEC 5200-001/6200-001 Lecture 7

  22. How Long Does It Take? • Assume control logic is fast and does not affect the critical timing. Major time delay components are ALU, memory read/write, and register read/write. • Arithmetic-type (R-type) • Fetch (memory read) 2ns • Register read 1ns • ALU operation 2ns • Register write 1ns • Total 6ns ELEC 5200-001/6200-001 Lecture 7

  23. Time for lw and sw (I-Types) • ALU (R-type) 6ns • Load word (I-type) • Fetch (memory read) 2ns • Register read 1ns • ALU operation 2ns • Get data (mem. Read) 2ns • Register write 1ns • Total 8ns • Store word (no register write) 7ns ELEC 5200-001/6200-001 Lecture 7

  24. Time for beq (I-Type) • ALU (R-type) 6ns • Load word (I-type) 8ns • Store word (I-type) 7ns • Branch on equal (I-type) • Fetch (memory read) 2ns • Register read 1ns • ALU operation 2ns • Total 5ns ELEC 5200-001/6200-001 Lecture 7

  25. Time for Jump (J-Type) • ALU (R-type) 6ns • Load word (I-type) 8ns • Store word (I-type) 7ns • Branch on equal (I-type) 5ns • Jump (J-type) • Fetch (memory read) 2ns • Total 2ns ELEC 5200-001/6200-001 Lecture 7

  26. How Fast Can the Clock Be? • If every instruction is executed in one clock cycle, then: • Clock period must be at least 8ns to perform the longest instruction, i.e., lw. • This is a single cycle machine. • It is slower because many instructions take less than 8ns but are still allowed that much time. • Method of speeding up: Use multicycle datapath. ELEC 5200-001/6200-001 Lecture 7

  27. A Single Cycle Example Delay of 1-bit full adder = 1ns Clock period ≥ 32ns a31 . . . a2 a1 a0 c32 1-b full adder s31 . . . s2 s1 s0 1-b full adder b31 . . . b2 b1 b0 1-b full adder 1-b full adder Time of adding words ~ 32ns Time of adding bytes ~ 32ns 0 ELEC 5200-001/6200-001 Lecture 7

  28. A Multicycle Implementation a31 . . . a2 a1 a0 Delay of 1-bit full adder = 1ns Clock period ≥ 1ns Time of adding words ~ 32ns Time of adding bytes ~ 8ns Shift 1-b full adder b31 . . . b2 b1 b0 s31 . . . s2 s1 s0 c32 FF Shift Shift Initialize to 0 ELEC 5200-001/6200-001 Lecture 7

  29. Multicycle Datapath Instr. reg. (IR) A Reg. PC Addr. Memory ALU Register file ALUOut Reg. Data 4 Mem. Data (MDR) B Reg. One-cycle data transfer paths (need registers to hold data) ELEC 5200-001/6200-001 Lecture 7

  30. Multicycle Datapath Requirements • Only one ALU, since it can be reused. • Single memory for instructions and data. • Five registers added: • Instruction register (IR) • Memory data register (MDR) • Three ALU registers, A and B for inputs and ALUOut for output ELEC 5200-001/6200-001 Lecture 7

  31. Multicycle Datapath PCSource PCWrite etc. Shift left 2 26-31 to Control FSM 0-25 RegWrite 21-25 28-31 16-20 Instr. reg. (IR) A Reg. PC Addr. 11-15 Memory ALU Register file ALUSrcA ALUSrcB ALUOut Reg. IorD Data Mem. Data (MDR) B Reg. out RegDst MUX control IRWrite 4 in1 in2 MemRead Sign extend Shift left 2 MemtoReg 0-15 MemWrite ALU control ALUOp 0-5 ELEC 5200-001/6200-001 Lecture 7

  32. 3 to 5 Cycles for an Instruction ELEC 5200-001/6200-001 Lecture 7

  33. Cycle 1 of 5: Instruction Fetch (IF) • Read instruction into IR, M[PC] → IR • Control signals used: • IorD = 0 select PC • MemRead = 1 read memory • IRWrite = 1 write IR • Increment PC, PC + 4 → PC • Control signals used: • ALUSrcA = 0 select PC into ALU • ALUSrcB = 01 select constant 4 • ALUOp = 00 ALU adds • PCSource = 00 select ALU output • PCWrite = 1 write PC ELEC 5200-001/6200-001 Lecture 7

  34. Cycle 2 of 5: Instruction Decode (ID) 31-26 25-21 20-16 15-11 10-6 5-0 R I J opcode | reg 1 | reg 2 | reg 3 | shamt | fncode • Control unit decodes instruction • Datapath prepares for execution • R and I types, reg 1→ A reg, reg 2 → B reg • No control signals needed • Branch type, compute branch address in ALUOut • ALUSrcA = 0 select PC into ALU • ALUSrcB = 11 Instr. Bits 0-15 shift 2 into ALU • ALUOp = 00 ALU adds opcode | reg 1 | reg 2 | word address increment opcode | word address jump ELEC 5200-001/6200-001 Lecture 7

  35. Cycle 3 of 5: Execute (EX) • R type: execute function on reg A and reg B, result in ALUOut • Control signals used: • ALUSrcA = 1 A reg into ALU • ALUsrcB = 00 B reg into ALU • ALUOp = 10 instr. Bits 0-5 control ALU • I type, lw or sw: compute memory address in ALUOut ← A reg + sign extend IR[0-15] • Control signals used: • ALUSrcA = 1 A reg into ALU • ALUSrcB = 10 Instr. Bits 0-15 into ALU • ALUOp = 00 ALU adds ELEC 5200-001/6200-001 Lecture 7

  36. Cycle 3 of 5: Execute (EX) • I type, beq: subtract reg A and reg B, write ALUOut to PC • Control signals used: • ALUSrcA = 1 A reg into ALU • ALUsrcB = 00 B reg into ALU • ALUOp = 01 ALU subtracts • If zero = 1, PCSource = 01 ALUOut to PC • If zero = 1, PCwriteCond =1 write PC • Instruction complete, go to IF • J type: write jump address to PC ← IR[0-25] shift 2 and four leading bits of PC • Control signals used: • PCSource = 10 • PCWrite = 1 write PC • Instruction complete, go to IF ELEC 5200-001/6200-001 Lecture 7

  37. Cycle 4 of 5: Reg Write/Memory • R type, write destination register from ALUOut • Control signals used: • RegDst = 1 Instr. Bits 11-15 specify reg. • MemtoReg = 0 ALUOut into reg. • RegWrite = 1 write register • Instruction complete, go to IF • I type, lw: read M[ALUOut] into MDR • Control signals used: • IorD = 1 select ALUOut into mem adr. • MemRead = 1 read memory to MDR • I type, sw: write M[ALUOut] from B reg • Control signals used: • IorD = 1 select ALUOut into mem adr. • MemWrite = 1 write memory • Instruction complete, go to IF ELEC 5200-001/6200-001 Lecture 7

  38. Cycle 5 of 5: Reg Write • I type, lw: write MDR to reg[IR(16-20)] • Control signals used: • RegDst = 0 instr. Bits 16-20 are write reg • MemtoReg = 1 MDR to reg file write input • RegWrite = 1 read memory to MDR • Instruction complete, go to IF For an alternative method of designing datapath, see N. Tredennick, Microprocessor Logic Design, the Flowchart Method, Digital Press, 1987. ELEC 5200-001/6200-001 Lecture 7

  39. 1-bit Control Signals zero(ALU) PCWriteCond PCWrite etc. PCWrite ELEC 5200-001/6200-001 Lecture 7

  40. 2-bit Control Signals ELEC 5200-001/6200-001 Lecture 7

  41. Control: Finite State Machine Start State 0 Clock cycle 1 Instruction fetch State 1 Clock cycle 2 Instruction decode and register fetch FSM-M Memory access instr. FSM-R FSM-B FSM-J Clock cycles 3-5 R-type instr. Branch instr. Jump instr. ELEC 5200-001/6200-001 Lecture 7

  42. State 0: Instruction Fetch (CC1) PCSource=00 PCWrite etc.=1 Shift left 2 26-31 to Control FSM 0-25 RegWrite 21-25 28-31 16-20 Instr. reg. (IR) A Reg. PC Addr. Memory ALU Register file ALUSrcB=01 ALUOut Reg. ALUSrcA=0 IorD=0 Data Mem. Data (MDR) B Reg. out RegDst MUX control IRWrite =1 4 Add in1 in2 MemRead = 1 Sign extend Shift left 2 MemtoReg 0-15 MemWrite ALUOp =00 ALU control 0-5 ELEC 5200-001/6200-001 Lecture 7

  43. MemRead =1 ALUSrcA = 0 IorD = 0 IRWrite = 1 ALUSrcB = 01 ALUOp = 00 PCWrite = 1 PCSource = 00 State 0 Control FSM Outputs Start State 1 Instruction decode/ Register fetch/ Branch addr. State0 Instruction fetch Outputs? ELEC 5200-001/6200-001 Lecture 7

  44. State 1: Instr. Decode/Reg. Fetch/ Branch Address (CC2) PCSource PCWrite etc. Shift left 2 26-31 to Control FSM 0-25 RegWrite 21-25 28-31 16-20 Instr. reg. (IR) A Reg. PC Addr. Memory ALU Register file ALUSrcA=0 ALUSrcB=11 ALUOut Reg. IorD Data Mem. Data (MDR) B Reg. out RegDst MUX control Add IRWrite 4 in1 in2 MemRead Sign extend Shift left 2 MemtoReg 0-15 MemWrite ALUOp = 00 ALU control 0-5 ELEC 5200-001/6200-001 Lecture 7

  45. MemRead =1 ALUSrcA = 0 IorD = 0 IRWrite = 1 ALUSrcB = 01 ALUOp = 00 PCWrite = 1 PCSource = 00 FSM-M FSM-R FSM-B FSM-J State 1 Control FSM Outputs Start State 1 Instruction decode (ID) / Register fetch / Branch addr. State0 Instruction fetch (IF) ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 Opcode = lw, sw Opcode = R-type Opcode = BEQ Opcode = J-type ELEC 5200-001/6200-001 Lecture 7

  46. State 1 (Opcode = lw) → FSM-M (CC3-5) PCSource CC4 PCWrite etc. Shift left 2 26-31 to Control FSM 0-25 RegWrite=1 21-25 28-31 16-20 CC3 Instr. reg. (IR) A Reg. PC Addr. Memory ALU Register file ALUSrcA=1 ALUSrcB=10 ALUOut Reg. IorD=1 Data Mem. Data (MDR) B Reg. out CC5 MUX control Add IRWrite 4 RegDst=0 in1 in2 MemRead=1 Sign extend Shift left 2 MemtoReg=1 0-15 MemWrite ALUOp = 00 ALU control 0-5 ELEC 5200-001/6200-001 Lecture 7

  47. State 1 (Opcode= sw)→FSM-M (CC3-4) CC4 PCSource PCWrite etc. Shift left 2 26-31 to Control FSM 0-25 RegWrite 21-25 28-31 16-20 CC3 Instr. reg. (IR) A Reg. PC Addr. Memory ALU Register file ALUSrcA=1 ALUSrcB=10 ALUOut Reg. IorD=1 Data Mem. Data (MDR) B Reg. out RegDst=0 MUX control Add IRWrite 4 CC4 in1 in2 MemRead Sign extend Shift left 2 MemtoReg 0-15 MemWrite=1 ALUOp = 00 ALU control 0-5 ELEC 5200-001/6200-001 Lecture 7

  48. FSM-M (Memory Access) From state 1 Opcode = “lw” or “sw” Compute mem addrress ALUSrcA =1 ALUSrcB = 10 ALUOp = 00 Opcode = “lw” Opcode = “sw” Read Memory data Write memory MemRead = 1 IorD = 1 MemWrite = 1 IorD = 1 Write register To state 0 (Instr. Fetch) RegWrite = 1 MemtoReg = 1 RegDst = 0 ELEC 5200-001/6200-001 Lecture 7

  49. State 1(Opcode=R-type)→FSM-R (CC3-4) PCSource PCWrite etc. Shift left 2 26-31 to Control FSM 0-25 RegWrite 21-25 28-31 16-20 Instr. reg. (IR) A Reg. PC Addr. Memory ALU Register file ALUSrcA=1 CC3 ALUSrcB=00 ALUOut Reg. 11-15 IorD Data Mem. Data (MDR) B Reg. out RegDst=0 MUX control IRWrite 4 “funct. code” CC4 in1 in2 MemRead Sign extend Shift left 2 MemtoReg=0 0-15 MemWrite ALUOp = 10 ALU control 0-5 ELEC 5200-001/6200-001 Lecture 7

  50. FSM-R (R-type Instruction) From state 1 Opcode = R-type ALU operation ALUSrcA =1 ALUSrcB = 00 ALUOp = 10 Write register To state 0 (Instr. Fetch) RegWrite = 1 MemtoReg = 0 RegDst = 1 ELEC 5200-001/6200-001 Lecture 7