ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2007 Computer Arithmetic (Chapter 3)

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ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2007 Computer Arithmetic (Chapter 3). Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu.

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### ELEC 5200-001/6200-001Computer Architecture and DesignFall 2007 Computer Arithmetic (Chapter 3)

Vishwani D. Agrawal

James J. Danaher Professor

Department of Electrical and Computer Engineering

Auburn University, Auburn, AL 36849

http://www.eng.auburn.edu/~vagrawal

vagrawal@eng.auburn.edu

ELEC 5200-001/6200-001 Lecture 11

What Goes on Inside ALU?
• Machine instr.: add \$t1, \$s1, \$s2
• What it means to computer:

000000 10001 10010 01000 00000 100000

Arithmetic Logic Unit

(ALU)

Control unit

Flags

Registers

Registers

ELEC 5200-001/6200-001 Lecture 11

Basic Idea
• Hardware can only deal with binary digits, 0 and 1.
• Must represent all numbers, integers or floating point, positive or negative, by binary digits, called bits.
• Devise electronic circuits to perform arithmetic operations, add, subtract, multiply and divide, on binary numbers.

ELEC 5200-001/6200-001 Lecture 11

Positive Integers
• Decimal system: made of 10 digits, {0,1,2, . . . , 9}

41 = 4×101 + 1×100

255 = 2×102 + 5×101 + 5×100

• Binary system: made of two digits, {0,1}

00101001 = 0×27 + 0×26 + 1×25 + 0×24 +1×23 +0×22 + 0×21 + 1×20

=32 + 8 +1 = 41

11111111 = 255, largest number with 8 binary digits, 28-1

ELEC 5200-001/6200-001 Lecture 11

• For decimal system, 10 is called the base or radix.
• Decimal 41 is also written as 4110 or 41ten
• Base (radix) for binary system is 2.
• Thus, 41ten = 1010012 or 101001two
• Also, 111ten = 1101111two

and 111two = 7ten

ELEC 5200-001/6200-001 Lecture 11

Signed Integers – What Not to Do
• Use fixed length binary representation
• Use left-most bit (called most significant bit or MSB) for sign:

0 for positive

1 for negative

• Example: +18ten = 00010010two

- 18ten = 10010010two

ELEC 5200-001/6200-001 Lecture 11

Why Not Use Sign Bit
• Sign and magnitude bits should be differently treated in arithmetic operations.
• Addition and subtraction require different logic circuits.
• Overflow is difficult to detect.
• “Zero” has two representations:

+0ten = 00000000two

- 0ten = 10000000two

• Signed-integers are not used in modern computers.

ELEC 5200-001/6200-001 Lecture 11

Integers With Sign – Other Ways
• Use fixed-length representation, but no sign bit
• 1’s complement: To form a negative number, complement each bit in the given number.
• 2’s complement: To form a negative number, start with the given number, subtract one, and then complement each bit, or

first complement each bit, and then add 1.

• 2’s complement is the preferred representation.

ELEC 5200-001/6200-001 Lecture 11

1’s-Complement
• To change the sign of a binary integer simply complement (invert) each bit.
• Example: 3 = 0011, – 3 = 1100
• n-bit representation: Negation is equivalent to subtraction from 2n – 1

Infinite

universe

-9 -6 -3 0 3 6 9

0 3 6 9 12 15

Modulo-16

universe

0 3 6

-6 -3 -0

0000 0011 0110 1001 1100 1111

ELEC 5200-001/6200-001 Lecture 11

2’s-Complement
• Add 1 to 1’s-complement representation.
• Some properties:
• Only one representation for 0
• Exactly as many positive numbers as negative numbers
• Slight asymmetry – there is one negative number with no positive counterpart

ELEC 5200-001/6200-001 Lecture 11

Three Representations

Sign-magnitude

000 = +0

001 = +1

010 = +2

011 = +3

100 = - 0

101 = - 1

110 = - 2

111 = - 3

1’s complement

000 = +0

001 = +1

010 = +2

011 = +3

100 = - 3

101 = - 2

110 = - 1

111 = - 0

2’s complement

000 = +0

001 = +1

010 = +2

011 = +3

100 = - 4

101 = - 3

110 = - 2

111 = - 1

(Preferred)

ELEC 5200-001/6200-001 Lecture 11

2’s Complement Numbers

000

-1

+1

0

-1

111

001

+1

Positive numbers

010

+2

Negative numbers

-2

110

011

+3

-3

101

- 4

100

Overflow

Negation

ELEC 5200-001/6200-001 Lecture 11

2’s Complement n-bit Numbers
• Range: –2n –1 through 2n –1 – 1
• Unique zero: 00000000 . . . . . 0
• Negation rule: see slide 9.
• Expansion of bit length: stretch the left-most bit all the way, e.g., 11111101 is still – 3.
• Overflow rule: If two numbers with the same sign bit (both positive or both negative) are added, the overflow occurs if and only if the result has the opposite sign.
• Subtraction rule: for A – B, add – B to A.

ELEC 5200-001/6200-001 Lecture 11

Converting 2’s Compliment to Decimal

n-2

an-1an-2 . . . a1a0 = -2n-1an-1 + Σ 2i ai

i=0

8-bit conversion box

-128 64 32 16 8 4 2 1

-128 64 32 16 8 4 2 1

1 1 1 1 1 1 0 1

Example

-128+64+32+16+8+4+1 = -128 + 125 = -3

ELEC 5200-001/6200-001 Lecture 11

For More on 2’s Complement
• Chapter 2 in D. E. Knuth, The Art of Computer Programming: Seminumerical Algorithms, Volume II, Second Edition, Addison-Wesley, 1981.
• A. al’Khwarizmi, Hisab al-jabr w’al-muqabala, 830.

Abu Abd-Allah ibn Musa al’Khwarizmi (~780 – 850)

Donald E. Knuth (1938 - )

ELEC 5200-001/6200-001 Lecture 11

MIPS
• MIPS architecture uses 32-bit numbers. What is the range of integers (positive and negative) that can be represented?

Positive integers: 0 to 2,147,483,647

Negative integers: - 1 to - 2,147,483,648

• What are the binary representations of the extreme positive and negative integers?

0111 1111 1111 1111 1111 1111 1111 1111 = 231 - 1= 2,147,483,647

1000 0000 0000 0000 0000 0000 0000 0000 = - 231 = - 2,147,483,648

• What is the binary representation of zero?

0000 0000 0000 0000 0000 0000 0000 0000

ELEC 5200-001/6200-001 Lecture 11

• 0 + 0 = 0
• 0 + 1 = 1
• 1 + 0 = 1
• 1 + 1 = (1) 0

carry

1 1 0

0 0 0 . . . . . . 0 1 1 1 two = 7ten

+ 0 0 0 . . . . . . 0 1 1 0 two = 6ten

= 0 0 0 . . . . . . 1 (1)1 (1)0 (0)1 two = 13ten

ELEC 5200-001/6200-001 Lecture 11

Subtraction
• Direct subtraction
• Two’s complement subtraction

0 0 0 . . . . . . 0 1 1 1 two = 7ten

- 0 0 0 . . . . . . 0 1 1 0 two = 6ten

= 0 0 0 . . . . . . 0 0 0 1two = 1ten

1 1 1 . . . . . . 1 1 0

0 0 0 . . . . . . 0 1 1 1 two = 7ten

+ 1 1 1 . . . . . . 1 0 1 0 two = - 6ten

= 0 0 0 . . . . . . 0 (1) 0 (1) 0 (0)1 two = 1ten

ELEC 5200-001/6200-001 Lecture 11

Overflow: An Error
• Examples: Addition of 3-bit integers (range - 4 to +3)
• -2-3 = -5110 = -2

+ 101 = -3

= 1011 = 3 (error)

• 3+2 = 5011 = 3

010 = 2

= 101 = -3 (error)

• Overflow rule: If two numbers with the same sign bit (both positive or both negative) are added, the overflow occurs if and only if the result has the opposite sign.

000

111

0

001

1

-1

010

– +

2

110

-2

3

-3

011

- 4

101

100

Overflow

ELEC 5200-001/6200-001 Lecture 11

Design Hardware Bit by Bit

a b half_sum carry_out

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

a

half_sum

XOR

b

carry_out

AND

ELEC 5200-001/6200-001 Lecture 11

a b ci half_sum carry_out sum co

0 0 0 0 0 0 0

0 0 1 0 0 1 0

0 1 0 1 0 1 0

0 1 1 1 0 0 1

1 0 0 1 0 1 0

1 0 1 1 0 0 1

1 1 0 0 1 0 1

1 1 1 0 1 1 1

ELEC 5200-001/6200-001 Lecture 11

ci

FAi

XOR

sumi

ai

XOR

AND

bi

AND

OR

Ci+1

ELEC 5200-001/6200-001 Lecture 11

c0

a0

b0

sum0

FA0

sum1

a1

b1

FA1

sum2

a2

b2

FA2

sum31

FA31

a31

b31

ELEC 5200-001/6200-001 Lecture 11

• Longest delay path (critical path) runs from cin to sum31.
• Suppose delay of full-adder is 100ps.
• Critical path delay = 3,200ps
• Clock rate cannot be higher than 1/(3,200×1012) Hz = 312MHz.
• Must use more efficient ways to handle carry.

ELEC 5200-001/6200-001 Lecture 11

a0-a15

16-bit

ripple

carry

b0-b15

cin

sum0-sum15

a16-a31

16-bit

ripple

carry

0

b16-b31

0

sum16-sum31

Multiplexer

a16-a31

16-bit

ripple

carry

1

b16-b31

1

ELEC 5200-001/6200-001 Lecture 11

• In general, any output of a 32-bit adder can be evaluated as a logic expression in terms of all 65 inputs.
• Number of levels of logic can be reduced to log2N for N-bit adder. Ripple-carry has N levels.
• More gates are needed, about log2N times that of ripple-carry design.

ELEC 5200-001/6200-001 Lecture 11

Reference: J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, Second Edition, San Francisco, California, 1990, page A-46.

ELEC 5200-001/6200-001 Lecture 11

MIPS Instructions (see p. 175)
• Data transfer: lw, sw, lhu, sh, lbu, sb, lui
• Logical: and, or, nor, andi, ori, sll, srl
• Conditional branch: beq, bne, slt, slti, sltu, sltiu
• Unconditional jump: j, jr, jal

ELEC 5200-001/6200-001 Lecture 11

Exception or Interrupt
• If an overflow is detected while executing add, addi or sub, then the address of that instruction is placed in a register called exception program counter (EPC).
• Instruction mfc0 can copy \$epc to any other register, e.g., mfc0 \$s1, \$epc
• Unsigned operations, addu, addiu and subu do not cause an exception or interrupt.

ELEC 5200-001/6200-001 Lecture 11

Multifunction ALU

operation

c0

a0

b0

result0

ALU0

result1

a1

b1

ALU1

result2

operation

a2

b2

ALU2

ci

ai

bi

FAi

3

NOR

2

resulti

mux

OR

1

result31

ALU31

a31

b31

AND

0

ELEC 5200-001/6200-001 Lecture 11

Who Said This?

“I’ve been waiting more than 30 years to say this: Dad, I always told you I’d come back and get my degree.”

ELEC 5200-001/6200-001 Lecture 11

“I’ve been waiting more than 30 years to say this: Dad, I always told you I’d come back and get my degree.”

ELEC 5200-001/6200-001 Lecture 11

Binary Multiplication (Unsigned)

1 0 0 0 two = 8ten multiplicand

1 0 0 1 two = 9ten multiplier

____________

1 0 0 0

0 0 0 0 partial products

0 0 0 0

1 0 0 0

____________

1 0 0 1 0 0 0two = 72ten

Basic algorithm: n = 1, 32

If nth bit of multiplier is 1,

Add multiplicand × 2 n –1

to product

ELEC 5200-001/6200-001 Lecture 11

Multiplication Flowchart

Start

Initialize product register to 0

Partial product number, n = 1

LSB

of multiplier

?

product and place result

in product register

1

0

Left shift multiplicand register 1 bit

Right shift multiplier register 1 bit

n = 32

n < 32

i = ?

Done

n = n + 1

ELEC 5200-001/6200-001 Lecture 11

Serial Multiplication

shift left

shift right

Multiplicand (expanded 64-bits)

32-bit multiplier

64

64

shift

Test LSB

32 times

64-bit ALU

LSB

= 1

LSB = 0

64

3 operations per bit:

shift right

shift left

Need 64-bit ALU

64-bit product register

write

ELEC 5200-001/6200-001 Lecture 11

Serial Multiplication (Improved)

Multiplicand

2 operations per bit:

shift right

32

32

1

Test LSB

32 times

32-bit ALU

LSB

1

32

write

64-bit product register

shift right

00000 . . . 00000 32-bit multiplier

Initialized prod. Reg.

ELEC 5200-001/6200-001 Lecture 11

Example: 0010two× 0011two

0010two× 0011two = 0110two, i.e., 2ten×3ten = 6ten

ELEC 5200-001/6200-001 Lecture 11

Signed Multiplication
• Convert numbers to magnitudes.
• Multiply the two magnitudes through 32 iterations.
• Negate the result if the signs of the multiplicand and multiplier differed.
• Alternatively, the previous algorithm will work with some modifications, listed next.

ELEC 5200-001/6200-001 Lecture 11

Multiplying 2’s Complement
• Use one extra bit for multiplicand addition.
• Extend sign bit in right shift (Examples 1 and 2).
• If multiplier is negative, then the last addition is replaced by subtraction (Example 2). Why? See slide 14.
• See B. Parhami, Computer Architecture, New York: Oxford University Press, 2005, pp. 199-200.

ELEC 5200-001/6200-001 Lecture 11

Example 1: 1010two× 0011two

1010two× 0011two = 101110two, i.e., -6ten×3ten = -18ten

ELEC 5200-001/6200-001 Lecture 11

Example 2: 1010two× 1011two

1010two× 1011two = 011110two, i.e., -6ten×(-5ten) = 30ten

*Last iteration with a negative multiplier in 2’s complement.

ELEC 5200-001/6200-001 Lecture 11

Booth Multiplier Algorithm
• A. D. Booth, “A Signed Binary Multiplication Technique,” Quarterly Journal of Mechanics and Applied Math., vol. 4, pt. 2, pp. 236-240, 1951.
• Direct multiplication of positive and negative integers using two’s complement addition.

ELEC 5200-001/6200-001 Lecture 11

A Multiplication Trick
• Consider decimal multiplication:

4 5 7

9 9 9 0 1

4 5 7

4 1 1 3

4 1 1 3

4 1 1 3

4 5 6 5 4 7 5 7 Three additions

• Operations for each digit of multiplier:
• Do nothing if the digit is 0
• Shift left, i.e., multiply by some power of 10
• Multiply by the digit, i.e., by a number between 1 and 9

ELEC 5200-001/6200-001 Lecture 11

What is the Trick?
• Examine multiplier:

99901 = 100000 – 100 + 1

• Multiply as follows:

457 × 100000 = 45700000

457 × ( - 100) = - 45700subtraction

45654300

45654757

Reduced from three to two operations.

ELEC 5200-001/6200-001 Lecture 11

Booth Algorithm: Basic Idea
• Consider a multiplier, 00011110 (30)
• We can write, 30 = 32 – 2, or

00100000 (32) = 25

+11111110 (–2) = –21

00011110(0) 30

• Interpret multiplier (scan right to left), check bit-pairs:
• kth bit is 1, (k-1)th bit is 0, multiplier contains -2k term
• kth bit is 0, (k-1)th bit is 1, multiplier contains 2kterm
• kth bit is 1, (k-1)th bit is 1, -2k is absent in multiplier
• kth bit is 0, (k-1)th bit is 0, 2k is absent in multiplier
• Product, M×30 = M×25 - M×21 M: multiplicand
• Multiplication by 2k means a k-bit left shift

ELEC 5200-001/6200-001 Lecture 11

Booth Algorithm: Example 1
• 7 × 3 = 21

0111 multiplicand = 7

×0011(0) multiplier = 3

11111001 bit-pair 10, add -7 in two’s com.

bit-pair 11, do nothing

bit-pair 00, do nothing

00010101 21

ELEC 5200-001/6200-001 Lecture 11

Booth Algorithm: Example 2
• 7 × (-3) = -21

0111 multiplicand = 7

×1101(0) multiplier = -3

11111001 bit-pair 10, add -7 in two’s com.

111001 bit-pair 10, add -7 in two’s com.

bit-pair 11, do nothing

11101011 - 21

ELEC 5200-001/6200-001 Lecture 11

Booth Algorithm: Example 3
• -7 × 3 = -21

1001 multiplicand = -7 in two’s com.

×0011(0)multiplier = 3

bit-pair 11, do nothing

bit-pair 00, do nothing

11101011 - 21

ELEC 5200-001/6200-001 Lecture 11

Booth Algorithm: Example 4
• -7 × (-3) = 21

1001 multiplicand = -7 in two’s com.

×1101(0)multiplier = -3 in two’s com.

1111001 bit-pair 01, add -7 in two’s com.

bit-pair 11, do nothing

00010101 21

ELEC 5200-001/6200-001 Lecture 11

Serial multiplication

Booth algorithm

00010100 20

×00011110 30

00000000

00010100

00010100

00010100

00010100

00000000

00000000

00000000________

000001001011000 600

00010100 20

×000111100 30

111111111101100

00000010100

__________________

0000001001011000 600

ELEC 5200-001/6200-001 Lecture 11

Faster Multiplication
• Using repeated additions, we need as many clocks as there are bits, say n, in multiplier.
• Multiplication can be done in one clock. Of course, the period of clock will have to be longer; but may not be as long as n times.

ELEC 5200-001/6200-001 Lecture 11

A Simple Design

Mplier_b1·Mcand

Mplier_b0·Mcand

32b

32b

Mplier_b2·Mcand

33b

p0

32b

Mplier_b3·Mcand

33b

p1

Clock period

32b

33b

p2

Mplier_b31·Mcand

32b

33b

p30

p31…p63

ELEC 5200-001/6200-001 Lecture 11

y3 y2 y1 y0 Multiplicand

x3 x2 x1 x0 Multiplier

________________________

x0y3 x0y2 x0y1 x0y0

carry← x1y3 x1y2 x1y1 x1y0 Partial

carry← x2y3 x2y2 x2y1 x2y0 Products

carry← x3y3 x3y2 x3y1 x3y0

__________________________________________________

p7 p6 p5 p4 p3 p2 p1 p0

ELEC 5200-001/6200-001 Lecture 11

Array Multiplier: Carry Forward

y3 y2 y1 y0 Multiplicand

x3 x2 x1 x0 Multiplier

________________________

x0y3 x0y2 x0y1 x0y0

x1y3 x1y2 x1y1 x1y0 Partial

x2y3 x2y2 x2y1 x2y0 Products

x3y3 x3y2 x3y1 x3y0

__________________________________________________

p7 p6 p5 p4 p3 p2 p1 p0

Note: Carry is added to the next partial product. Adding the carry

from the final stage needs an extra stage. These additions are

faster but we need four stages.

ELEC 5200-001/6200-001 Lecture 11

Basic Building Blocks
• Two-input AND

yi xk

kth

partial

product

carry bits

from (k-1)th

product

yi x0

Full

p0i = x0yi

0th partial product

carry bits

to (k+1)th

product

(k+1)th partial

product

ELEC 5200-001/6200-001 Lecture 11

y3 y2 y1 y0

Array Multiplier

x0

ppk

yj

xi

0

x1

ci

0

0

0

0

0

FA

x2

co

ppk+1

0

x3

Critical path

0

0

FA

FA

FA

FA

p3

p2

p1

p0

p7

p6

p5

p4

ELEC 5200-001/6200-001 Lecture 11

Types of Array Multipliers
• Baugh-Wooley Algorithm: Signed product by two’s complement addition or subtraction according to the MSB’s.
• Booth multiplier algorithm
• Tree multipliers
• Reference: N. H. E. Weste and D. Harris, CMOS VLSI Design, A Circuits and Systems Perspective, Third Edition, Boston: Addison-Wesley, 2005.

ELEC 5200-001/6200-001 Lecture 11

MIPS Multiply Instructions
• Separate 32-bit registers, Hi and Lo, to hold the 64-bit product.
• Multiply signed:

mult \$s1, \$s2 # \$s1 × \$s2 = Hi, Lo

• Multiply unsigned:

multu \$s1, \$s2 # \$s1 × \$s2 = Hi, Lo

• Product is copied into registers by
• mfhi \$s1 # copies Hi into \$s1
• mflo \$s1 # copies Lo into \$s1

ELEC 5200-001/6200-001 Lecture 11

Binary Division (Unsigned)

1 3 Quotient

1 1 / 1 4 7 Divisor / Dividend

1 1

3 7 Partial remainder

3 3

4 Remainder

0 0 0 0 1 1 0 1

1 0 1 1 / 1 0 0 1 0 0 1 1

1 0 1 1

0 0 1 1 1 0

1 0 1 1

0 0 1 1 1 1

1 0 1 1

1 0 0

ELEC 5200-001/6200-001 Lecture 11

Binary Division (Unsigned), 4-bits

0 0 0 1

0 0 0 0 1 1 0

1 1 0 0

1 1 0 0 negative →quotient bit 0

0 1 0 0→restore remainder

0 0 0 0 1 1 0

1 1 0 0

1 1 0 1 negative →quotient bit 0

0 1 0 0→restore remainder

0 0 0 1 1 0

1 1 0 0

1 1 1 1 negative →quotient bit 0

0 1 0 0→restore remainder

0 0 1 1 0

1 1 0 0

00 1 0positive →quotient bit 1

• Dividend: 6 = 0110
• Divisor: 4 = 0100
• 4 = 1100
• 6
• ─ = 1, remainder 2
• 4

Iteration 4 Iteration 3 Iteration 2 Iteration 1

ELEC 5200-001/6200-001 Lecture 11

Binary Division Flowchart

Start

\$R=0, \$M=Divisor, \$Q=Dividend, count=n

\$R (33 b) | \$Q (32 b)

Shift 1-bit left \$R, \$Q

\$R and \$M have

one extra sign bit

beyond 32 bits.

\$R ← \$R - \$M

No

Yes

\$R < 0?

\$Q0=0

\$R←\$R+\$M

\$Q0=1

Restore \$R

(remainder)

count = count - 1

Done

\$Q=Quotient

\$R= Remainder

No

count = 0?

Yes

ELEC 5200-001/6200-001 Lecture 11

Example: 6/4 = 1, Remainder 2

Remainder | Quotient

ELEC 5200-001/6200-001 Lecture 11

Division

33-bit \$M (Divisor)

Step 2: Subtract \$R← \$R - \$M

33

33

33-bit ALU

Step 1: 1- bit left shift \$R and \$Q

32 times

33

33-bit \$R (Remainder)

32-bit \$Q (Dividend)

Step 3: If sign-bit (\$R)=0, set Q0=1

If sign-bit (\$R)=1, set Q0=0 and restore \$R

Initialize

\$R←0

V. C. Hamacher, Z. G. Vranesic and S. G. Zaky, Computer Organization, Fourth Edition,

New York: McGraw-Hill, 1996.

ELEC 5200-001/6200-001 Lecture 11

Example: 8/3 = 2, Remainder = 2

Initialize \$R = 0 0 0 0 0 \$Q = 1 0 0 0 \$M = 0 0 0 1 1

Step 1, L-shift \$R,Q = 0 0 0 0 1 \$Q = 0 0 0 0

Step 2, Add - \$M = 1 1 1 0 1

\$R = 1 1 1 1 0

Step 3, Set Q0 \$Q = 0 0 0 0

Restore + \$M = 0 0 0 1 1

\$R = 0 0 0 0 1

Step 1, L-shift \$R,Q = 0 0 0 1 0 \$Q = 0 0 0 0 \$M = 0 0 0 1 1

Step 2, Add - \$M = 1 1 1 0 1

\$R = 1 1 1 1 1

Step 3, Set Q0 \$Q = 0 0 00

Restore + \$M = 0 0 0 1 1

\$R = 0 0 0 1 0

Iteration 1

Iteration 2

ELEC 5200-001/6200-001 Lecture 11

Example: 8/3 = 2 (Remainder=2) (Continued)

\$R = 0 0 0 1 0 \$Q = 0 0 0 0 \$M = 0 0 0 1 1

Step 1, L-shift \$R ,Q = 0 0 1 0 0 \$Q = 0 0 0 0\$M = 0 0 0 1 1

Step 2, Add - \$M = 1 1 1 0 1

\$R = 0 0 0 0 1

Step 3, Set Q0 \$Q = 0 0 0 1

Step 1, L-shift \$R,Q = 0 0 0 1 0 \$Q = 00 1 0 \$M = 0 0 0 1 1

Step 2, Add - \$M = 1 1 1 0 1

\$R = 1 1 1 1 1

Step 3, Set Q0 \$Q = 00 1 0Final quotient

Restore + \$M = 0 0 0 1 1

\$R = 0 0 0 1 0

Iteration 3

Iteration 4

Remainder

Note “Restore \$R” in Steps 1, 2 and 4. This method is known as

the RESTORING DIVISION.

ELEC 5200-001/6200-001 Lecture 11

Deriving a Better Algorithm (1)

Start

\$R=0, \$M=Divisor, \$Q=Dividend, count=n

Shift 1-bit left \$R, \$Q

\$R (33 b)|\$Q (32 b)

\$R and \$M have

one extra sign bit

beyond 32 bits.

Reexamine the

restoring algorithm

from slide 61

\$R ← \$R - \$M

No

Yes

\$R < 0?

\$Q0=0

\$R←\$R+\$M

\$Q0=1

Restore \$R

(remainder)

Cycle contains

count = count - 1

Done

\$Q=Quotient

\$R= Remainder

No

count = 0?

Yes

ELEC 5200-001/6200-001 Lecture 11

Deriving a Better Algorithm (2)

Start

\$R=0, \$M=Divisor, \$Q=Dividend, count=n

Shift 1-bit left \$R, \$Q

\$R (33 b)|\$Q (32 b)

\$R ← \$R - \$M

No

\$R < 0?

Yes

\$Q0=1

\$Q0=0

No

Yes

Restore \$R

(remainder)

\$R < 0?

Rearrange

flowchart

\$R←\$R+\$M

count = count - 1

Done

\$Q=Quotient

\$R= Remainder

No

count = 0?

Yes

ELEC 5200-001/6200-001 Lecture 11

Deriving a Better Algorithm (3)

Start

\$R=0, \$M=Divisor, \$Q=Dividend, count=n

Shift 1-bit left \$R, \$Q

\$R (33 b)|\$Q (32 b)

\$R ← \$R - \$M

No

\$R < 0?

Yes

\$Q0=1

\$Q0=0

Rearrange

flowchart

count = count - 1

No

No

count = 0?

Yes

No

\$R < 0?

\$R < 0?

Yes

Yes

Restore \$R

(remainder)

Restore \$R

(remainder)

Done

\$Q=Quotient

\$R= Remainder

\$R←\$R+\$M

\$R←\$R+\$M

ELEC 5200-001/6200-001 Lecture 11

Deriving a Better Algorithm (4)

Start

\$R=0, \$M=Divisor, \$Q=Dividend, count=n

\$R,\$Q = a

\$M = b

Yes

\$R < 0?

\$R←\$R+\$M

Rearrange

flowchart

Restore \$R

(remainder)

No

Shift 1-bit left \$R, \$Q

\$R (33 b)|\$Q (32 b)

\$R ← \$R - \$M

(a + b)2 – b

= 2a + b

2a – b

No

\$R < 0?

Yes

\$Q0=1

\$Q0=0

Restore \$R

(remainder)

count = count - 1

No

Yes

No

count = 0?

\$R < 0?

Yes

Restore \$R

(remainder)

Done

\$Q=Quotient

\$R= Remainder

\$R←\$R+\$M

ELEC 5200-001/6200-001 Lecture 11

Deriving a Better Algorithm (4)

Start

\$R=0, \$M=Divisor, \$Q=Dividend, count=n

\$R (33 b)|\$Q (32 b)

\$R,#Q = a

\$M = b

No

Yes

\$R < 0?

Shift 1-bit left \$R, \$Q

Shift 1-bit left \$R, \$Q

Functional

equivalence

\$R ← \$R - \$M

\$R←\$R+\$M

2a – b

2a + b

No

\$R < 0?

Yes

\$Q0=1

\$Q0=0

count = count - 1

No

No

Yes

count = 0?

\$R < 0?

Yes

Restore \$R

(remainder)

Done

\$Q=Quotient

\$R= Remainder

\$R←\$R+\$M

ELEC 5200-001/6200-001 Lecture 11

Non-Restoring Division Algorithm

Start

\$R=0, \$M=Divisor, \$Q=Dividend, count=n

\$R (33 b)|\$Q (32 b)

No

Yes

\$R < 0?

Shift 1-bit left \$R, \$Q

Shift 1-bit left \$R, \$Q

\$R ← \$R - \$M

\$R←\$R+\$M

No

\$R < 0?

Yes

\$Q0=1

\$Q0=0

Cycle

contains

count = count - 1

No

No

Yes

count = 0?

\$R < 0?

Yes

Restore \$R

(remainder)

Done

\$Q=Quotient

\$R= Remainder

\$R←\$R+\$M

ELEC 5200-001/6200-001 Lecture 11

Non-Restoring Division
• Avoids the addition in the restore operation – does exactly one add or subtract per cycle.
• Non-restoring division algorithm:
• Step 1: Repeat 32 times
• if sign bit of \$R is 0

Left shift \$R,Q one-bit and subtract, \$R ← \$R - \$M

else (sign bit of \$R is 1)

Left shift \$R,Q one-bit and add, \$R ← \$R + \$M

• if sign bit of resulting \$R is 0

Set Q0 = 1

else (sign bit of resulting \$R is 1)

Set Q0 = 0

• Step 2: (after 32 Step 1 iterations) if sign bit of \$R is 1, add \$R ← \$R + \$M

ELEC 5200-001/6200-001 Lecture 11

Non-Restoring Division: 8/3 = 2 (Rem=2)

Initialize \$R = 0 0 0 0 0 \$Q = 1 0 0 0 \$M = 0 0 0 1 1

Step 1, L-shift \$R,Q = 0 0 0 0 1 \$Q = 0 0 0 ? \$M = 0 0 0 1 1

Subtract - \$M = 1 1 1 0 1

\$R = 1 1 1 1 0 \$Q = 0 0 0 0

Step 1, L-shift \$R,Q = 1 1 1 0 0 \$Q = 0 0 0? \$M = 0 0 0 1 1

Add +\$M = 0 0 0 1 1

\$R = 1 1 1 1 1 \$Q = 0 0 0 0

Step 1, L-shift \$R,Q = 1 1 1 1 0 \$Q = 0 0 0 ? \$M = 0 0 0 1 1

Add +\$M = 0 0 0 1 1

\$R = 0 0 0 0 1 \$Q = 0 0 01

Step 1, L-shift \$R,Q = 0 0 0 1 0 \$Q = 0 0 1 ? \$M = 0 0 0 1 1

Subtract -\$M = 1 1 1 0 1

\$R = 1 1 1 1 1 \$Q = 0 0 10Final quotient

Step 2, Add \$R ← \$R + \$M = 11111+00011 = 00010 (Final remainder)

Initialize \$R = 0 0 0 0 0 \$Q = 1 0 0 0 \$M = 0 0 0 1 1

Step 1, L-shift \$R,Q = 0 0 0 0 1 \$Q = 0 0 0 ?\$M = 0 0 0 1 1

Subtract - \$M = 1 1 1 0 1

\$R = 1 1 1 1 0 \$Q = 0 0 0 0

Step 1, L-shift \$R,Q = 1 1 1 0 0 \$Q = 0 0 0 ? \$M = 0 0 0 1 1

Add +\$M = 0 0 0 1 1

\$R = 1 1 1 1 1 \$Q = 0 0 00

Step 1, L-shift \$R,Q = 1 1 1 1 0 \$Q = 0 0 0? \$M = 0 0 0 1 1

Add +\$M = 0 0 0 1 1

\$R = 0 0 0 0 1 \$Q = 0 0 01

Step 1, L-shift \$R,Q = 0 0 0 1 0 \$Q = 0 0 1?\$M = 0 0 0 1 1

Subtract -\$M = 1 1 1 0 1

\$R = 1 1 1 1 1 \$Q = 0 0 10Final quotient

Step 2, Add \$R ← \$R + \$M = 11111+00011 = 00010 (Final remainder)

Iteration 1

Iteration 2

Iteration 3

Iteration 4

ELEC 5200-001/6200-001 Lecture 11

Signed Division
• Remember the signs and divide magnitudes.
• Negate the quotient if the signs of divisor and dividend disagree.
• There is no other direct division method for signed division.

ELEC 5200-001/6200-001 Lecture 11

MIPS Division
• div \$s2, \$s3 # Lo = quotient

# Hi = remainder

• divu \$s2, \$s3 # Lo = quotient

# Hi = remainder

• mflo and mfhi retrieve registers Lo and Hi

mflo rdst # move from Lo to rdst

mfhi rdst # move from Hi to rdst

• Hardware ignores overflow, so software should determine if the quotient is too large.
• Software should also check if divisor = 0.

ELEC 5200-001/6200-001 Lecture 11