Computer Architecture and Design ELEC 5200/6200 VHDL Tutorial

Computer Architecture and DesignELEC 5200/6200VHDL Tutorial Director: Dr. Vishwani D. Agrawal GTA: Jia Yao (jzy0001@auburn.edu)

Hardware Description Language • VHDL (VHSIC HDL) • VHSIC: Very High Speed Integrated circuit • Developed by U.S. DOD in mid-1980’s • IEEE standard 1076-1987/1993/200x • Based on Ada language • Verilog • Developed by Gateway Design Automation in 1984 (merged with Cadence) • IEEE Standard 1364-1995/2001/2005 • Based on C language

VHDL In Design Process • Model and Design digital circuits • Structural model: lists components and their interconnections • Behavioral model: describes behavior of the design and I/O response • Verify circuit design via simulation • Synthesize circuits from HDL models to real hardware implementation

VHDL Model • Entity Declaration • Defines the I/O of the model • Architectural body • Describes the operation of the model by describing behaviors or listing structures 1 bit full adder a cout b sum cin

1bit Full Adder Behavior Models Entity adder is port (a, b, cin: in std_logic; sum, cout: out std_logic); End entity adder; Architecture beh of adder is Begin D=a & b & cin; Process (D) Begin case (D) is when “000” => sum<=‘0’; cout <=‘0’; when “001” => sum<=‘1’; cout <=‘0’; ….. end case; end process; End architecture beh; Entity adder is port (a, b, cin: in std_logic; sum, cout: out std_logic); End entity adder; Architecture beh of adder is Begin sum <= a xor b xorcin; cout <= (a and b) or (a and cin) or (b and cin); End architecture beh;

1bit Full Adder Structural Model Component xor2 Port (in1, in2: in std_logic; out1: out std_logic); End component xor2; Signal s1, s2, s3, s4,s5: std_logic; Begin u0: xor2 port map (a, b, s1); u1:xor2 port map (s1,cin, sum); u2: and2 port map (a, b, s2); u3: and2 port map (a, cin, s3); u4: and2 port map (b, cin, s4); u5: or2 port map (s2, s3, s5); u6: or2 port map (s5, s4,cout); End Architecture str; Entity adder is port (a, b, cin: in std_logic; sum, cout: out std_logic); End entity adder; Architecture str of adder is Component and2 Port (in1, in2: in std_logic; out1: out std_logic); End component and2; Component or2 Port (in1, in2: in std_logic; out1: out std_logic); End component or2;

VHDL Format -- Entity • Entity Entityentity_nameis: port ( port_name(s): mode signal_type; …… port_name(s): mode signal_type); End entity entity_name; • Mode in: data flows into portout: data flows out of port only buffer: data flows out of port as well as internal feedback in-out: bi-directional • Signal_typebit: single bit signal, ‘0’ or ‘1’ bit_vector: array of bit signals, ‘0’ or ‘1’ std_logic: same as bit but for standard simulation and synthesis (IEEE standard 1164) std_logic_vector: array of std_logic signals Entity adder is port (a, b, cin: in std_logic; sum, cout: out std_logic); End entity adder;

VHDL Format – Entity • IEEE Standard 1164 Data types • must include IEEE library and package before entity declaration library IEEE; use IEEE.std_logic_1164.all; • std_logic and std_logic_vector have the following data types: ‘U’, ‘X’ – uninitialized/unknown ‘0’, ‘1’ – strongly-driven 0/1 ‘L’, ‘H’ – weakly-driven 0/1 (resistive) ‘Z’, ‘W’ – strong/weak “floating” ‘-’ – don’t care

VHDL Format – Architecture Architecturearchitecture_nameof entity_nameis -- internal signal declarations -- component declarations -- function and procedure declarations Begin -- component instantiations -- concurrent statements -- processes for sequential statements End architecture architecture_name;

VHDL Format – Architecture • Architecture example: basic concurrent statements • Concurrent statements execute at the same time Architecture beh of adder is Begin sum <= a xor b xorcin; cout <= (a and b) or (a and cin) or (b and cin); End architecture beh; the most basic concurrent statements

VHDL Format – Architecture • Architecture example: processes • Statements inside of process execute sequentially Internal signal declaration Architecture beh of adder is signal D: std_logic_vector (3 down to 0); Begin D=a & b & cin; Process (D) Begin case (D) is when “000” => sum<=‘0’; cout <=‘0’; when “001” => sum<=‘1’; cout <=‘0’; ….. end case; end process; End architecture beh; Process for sequential statements

VHDL Format – Architecture • Architecture example: Hierarchical models Must include component declarations and component instantiations in architecture body to incorporate hierarchy in VHDL Architecture str of adder is Component and2 Port (in1, in2: in std_logic; out1: out std_logic); End component and2; …. Begin u2: and2 port map (a, b, s2); u3: and2 port map (a, cin, s3); ... End Architecture str; Component declarations Component instantiations

VHDL Format – Process Construct • Process format process (sensitivity list) declarations begin sequential statements end process; • Sequential statements have to be included inside of process: If-then-else, case statements, while loops and for loops • Any change in the value of signals in the sensitivity list will cause the execution of process • The statements inside of a process are executed sequentially. • Process is concurrent statement

Sequential Statements In Process • If-then-else if conditionthen(... sequence of statements...) elsifconditionthen(... sequence of statements...)else(... sequence of statements...)end if; • Case caseexpression is whenchoices => sequence of statementswhenchoices => sequence of statements ... whenothers => sequence of statementsend case;

Sequential Statements In Process • while loop whileconditionloop... sequence of statements ... end loop; • For loop forloop_variableinrangeloop... sequence of statements... end loop;

Example: Modeling DFF in VHDL D Entity DFF is Port (D: in std_logic_vector(3 downto 0); clk, clr: in std_logic; Q: out std_logic_vector(3 downto 0)); End entity DFF; Architecture beh of DFF is Begin process (clk, clr, D) begin if (clr=‘0’) then Q <=“0000”; elsif (clk'event and clk='1') then Q <= D; end if; end process; End architecture beh; Q clk clr

Example: Modeling Moore FSM • Design a Moore FSM with • 4 states (s0 – s3) • Active high synchronous reset • Active high synchronous enable (EN): when EN=0, FSM holds its state unless reset; when EN=1, FSM cycles to the next state on rising edge of clock signal, i.e. s0 – s1 – s2 – s3 – s0 • 2 outputs (C1 and C0) giving the binary value of the current state, with C1 being the MSB, i.e. when @s0, C1= 0, C0=0, when @s2, C1=1, C0=0

Entity MOOREFSM is port ( RST, EN, CLK : in std_logic; C : out std_logic_vector (1 downto 0)); End entity MOOREFSM; Architecture beh of MOOREFSM is signal s : std_logic_vector (1 downto 0) := "00"; begin process(CLK, RST, EN) begin if (CLK' event and CLK='1') then if (RST = '1') then s <= "00"; elsif (EN = '1') then s <= s+1; end if; end if; end process; C <= s; end architecture beh;

References • [1] Nitin, Yogi, “Review of VHDL”, http://www.eng.auburn.edu/~vagrawal/COURSE/E6200_Fall09/course.html • [2] Charles E. Stroud, ELEC4200 class documents http://www.eng.auburn.edu/~strouce/elec4200.html • [3] Jan Van der Spiegel ,“VHDL tutorial’’, http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html • [4] LeonardoSpectrum for Altera HDL Synthesis Manual http://www.eng.auburn.edu/~vagrawal/COURSE/E6200_Spr09/PROJECT/VHDLSynthesisGuide.pdf

Computer Architecture and Design ELEC 5200/6200 VHDL Tutorial