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EE466: VLSI Design. 2009 Term Project. Expectation. To introduce you to basic research ideas Involves reading research paper Extraction of relevant parameters Simulation of circuits Presentation of results. Low Swing Signaling. Ideas Low Swing Signaling Reasons? Crosstalk

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ee466 vlsi design

EE466: VLSI Design

2009 Term Project

expectation
Expectation
  • To introduce you to basic research ideas
  • Involves reading research paper
  • Extraction of relevant parameters
  • Simulation of circuits
  • Presentation of results
low swing signaling
Low Swing Signaling
  • Ideas
    • Low Swing Signaling
      • Reasons?
    • Crosstalk
    • Performance metrics
    • Power dissipation metrics
low swing signaling1
Low Swing Signaling
  • Low Swing Interconnect Interface Circuits
  • Hui Zhang & Jan Rabaey
  • 2 Circuits to compare
basic idea
Basic Idea
  • Interface circuits
interfaces
Interfaces
  • Conventional Level Converter (CLC)
    • Reference
  • Symmetric Source-Follower Driver with Level Converter (SSDLC)
  • Level Converting Register (LCR)
slide7
CLC
  • VddL is the low swing reference voltage
  • Uses static devices
ssdlc
SSDLC
  • Swing is limited between Vtn and Vdd-Vtn
slide9
LCR
  • REF voltage limits the swing
goals
Goals
  • Simulate Circuits
  • Consider a 3 wire bus
    • Apply similar interface circuits on neighbors
    • Study all crosstalk patterns
    • Evaluate average delay on victim
    • Evaluate worst case delay on victim
  • Compute power and energy dissipation
    • Present energy delay product metrics
milestones
Milestones
  • Reading Material
    • Papers for reading on website
  • Design of interface circuits
  • Understand wire parameter extraction
    • Reading material will be provided
      • Technology and Reliability Constrained Copper Interconnects Part II: Performance Implications
    • Study crosstalk effects
  • Present report with relevant metrics
deadlines
Deadlines
  • Final submission
    • Day of final exam
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