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Pass Transistor Logic. Agenda. Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated Electronics Static CMOS Logic Circuits Pseudo nMOS Logic Circuits Pass Transistor Logic Circuits Dynamic Logic Circuits Case Studies.

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Presentation Transcript
agenda
Agenda
  • Introduction
  • VLSI Design methodologies
  • Review of MOS Transistor Theory
  • Inverter – Nucleus of Digital Integrated Electronics
  • Static CMOS Logic Circuits
  • Pseudo nMOS Logic Circuits
  • Pass Transistor Logic Circuits
  • Dynamic Logic Circuits
  • Case Studies
pass transistor logic circuits
Pass Transistor Logic Circuits
  • nMOS Pass transistor – transmission properties
  • Transmission Gates
  • Transmission Gate Applications
    • Mux
    • XOR
    • D Latch
    • D Flip Flop
    • Clock Skew management
  • Pass Transistor Logic Families
pass transistor logic circuits8
PASS TRANSISTOR LOGIC CIRCUITS
  • nMOS Pass transistor – transmission properties
  • Transmission Gates
  • Transmission Gate Applications
    • Mux
    • XOR
    • D Latch
    • D Flip Flop
    • Clock Skew management
  • Pass Transistor Logic Families
transmission gates
TRANSMISSION GATES
  • NMOS pass transistor passes a strong 0 and a weak 1.
  • PMOS pass transistor passes a strong 1 and a weak 0.
  • Combine the two to make a CMOS pass gate which will

pass a strong 0 and a strong 1.

problems with transmission gates
PROBLEMS WITH TRANSMISSION GATES
  • No isolation between the input and output.
  • Output progressively deteriorates as it passes through various stages.

However designs get simplified.

pass transistor logic circuits13
PASS TRANSISTOR LOGIC CIRCUITS
  • nMOS Pass transistor – transmission properties
  • Transmission Gates
  • Transmission Gate Applications
    • Mux
    • XOR
    • D Latch
    • D Flip Flop
    • Clock Skew management
  • Pass Transistor Logic Families
pass transistor logic circuits15
Pass Transistor Logic Circuits
  • nMOS Pass transistor – transmission properties
  • Transmission Gates
  • Transmission Gate Applications
    • Mux
    • XOR
    • D Latch
    • D Flip Flop
    • Clock Skew management
  • Pass Transistor Logic Families
pass transistor logic circuits17
PASS TRANSISTOR LOGIC CIRCUITS
  • nMOS Pass transistor – transmission properties
  • Transmission Gates
  • Transmission Gate Applications
    • Mux
    • XOR
    • D Latch
    • D Flip Flop
    • Clock Skew management
  • Pass Transistor Logic Families
pass transistor logic circuits23
PASS TRANSISTOR LOGIC CIRCUITS
  • nMOS Pass transistor – transmission properties
  • Transmission Gates
  • Transmission Gate Applications
    • Mux
    • XOR
    • D Latch
    • D Flip Flop
    • Clock Skew management
  • Pass Transistor Logic Families
static flip flop
Static Flip Flop

Clk

Clk

D

0

1

Q

1

0

Transparent when Clk=0

Transparent when Clk=1

At Clk= 0  1, Q = D. Else Q is held.

pass transistor logic circuits28
Pass Transistor Logic Circuits
  • nMOS Pass transistor – transmission properties
  • Transmission Gates
  • Transmission Gate Applications
    • Mux
    • XOR
    • D Latch
    • D Flip Flop
    • Clock Skew management
  • Pass Transistor Logic Families
handling clock skew
Handling Clock Skew

Clk-in

Clk

Clk'

pass transistor logic circuits30
Pass Transistor Logic Circuits
  • nMOS Pass transistor – transmission properties
  • Transmission Gates
  • Transmission Gate Applications
    • Mux
    • XOR
    • D Latch
    • D Flip Flop
    • Clock Skew management
  • Pass Transistor Logic Families
pass transistor logic families
Pass Transistor Logic Families
  • Complementary Pass Transistor Logic Family
  • Dual Pass Transistor Logic Family
  • Swing Restored Pass Transistor Logic Family
problems
Problems
  • Design 4 to 1 multiplexor using transmission-gates.
  • Implement an XOR gate using minimum number of transistors.
  • Implement a full adder using transmission gates.
solution 1
Solution - 1

C1

C'0

A0

C0

C'1

A1

Y

A2

A3

solution 2
Solution - 2

C'0

A0

C0

C'1

A1

C1

Y

A2

A3

xor gate35
XOR Gate

A

B

AB