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The NS7520. NET+ARM. ARM7TDMI Programmer’s Model. Processor Operating States.

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net arm
NET+ARM

ARM7TDMI

Programmer’s Model

processor operating states
Processor Operating States
  • The ARM7TDMI can be in one of two Processor Operating States:- ARM state which executes 32-bit, word-aligned ARM instructions- Thumb state which operates with 16-bit, halfword-aligned Thumb instructions.Note: Transition between these two states does notaffect the operating mode (user, supervisor, …) or the contents of the registers
switching between op states
Switching between OP States
  • Entering Thumb state:- Execute a BX instruction with the state bit (bit 0) set in the operand register- Transition also occurs automatically when returning from an exception if this was entered with the processor in Thumb state
  • Entering ARM state- Execute a BX instruction with the state bit clear in the operand register- Also occurs on the processor taking an exception (IRQ, FIQ, RESET, UNDEF, ABORT, SWI, etc.)

BX = Branch and Exchange (Operating State)

memory formats
Memory Formats
  • ARM7TDMI views memory as a linear collection of bytes numbered upwards from zero.
  • Bytes 0 to 3 hold the first word, bytes 4 to 7 the second and so on.
  • The ARM7TDMI can treat words in memory as being stored either in - Big Endian format (also known as Motorola format)- Little Endian format (also known as Intel format)
big endian format
Big Endian Format

Higher Address

Word Address

31

24

23

16

15

8

7

0

8

9

10

11

8

4

5

6

7

4

0

1

2

3

0

Lower Address

  • Most Significant Byte is at lowest address
  • Word is addressed by byte address of most significant byte
little endian format
Little Endian Format

Higher Address

Word Address

31

24

23

16

15

8

7

0

11

10

9

8

8

7

6

5

4

4

3

2

1

0

0

Lower Address

  • Least Significant Byte is at lowest address
  • Word is addressed by byte address of least significant byte
instruction length and data types
Instruction Length and Data Types
  • ARM7TDMI Instruction Length is- 32 bits in ARM state- 16 bit in Thumb state
  • ARM7TDMI supported datatypes are:- byte (8-bit)- halfword (16-bit)- word (32-bit)
  • Words must be aligned to four-byte boundaries and halfwords at two-byte boundaries
arm7tdmi registers
ARM7TDMI Registers
  • ARM7TDMI has a total of 37 registers- 31 general purpose 32-bit registers- 6 status registers
  • Not all registers can be seen at once!
  • The processor state and operating mode dictate which registers are available to the programmer
arm state register set
ARM State Register Set
  • 16 general registers and one or two status registers are visible at one time
  • Mode-specific banked registers are switched inin privileged, non-User modes
  • Dedicated registers are:- R14 receives a copy of R15 when a Branch with Link instruction (BL) is executed.- R15 holds the Program Counter- R16 is the CPSR (Current Program Status Register) This contains the condition code flags and the current mode bits.
arm state register set1
ARM State Register Set

System & User

FIQ

Supervisor

Abort

IRQ

Undefined

R0

R0

R0

R0

R0

R0

R1

R1

R1

R1

R1

R1

R2

R2

R2

R2

R2

R2

R3

R3

R3

R3

R3

R3

R4

R4

R4

R4

R4

R4

R5

R5

R5

R5

R5

R5

R6

R6

R6

R6

R6

R6

R7

R7

R7

R7

R7

R7

R8

R8_fiq

R8

R8

R8

R8

R9

R9_fiq

R9

R9

R9

R9

R10

R10_fiq

R10

R10

R10

R10

R11

R11_fiq

R11

R11

R11

R11

R12

R12_fiq

R12

R12

R12

R12

SP

SP_fiq

SP_svc

SP_abt

SP_irq

SP_und

LR

LR_fiq

LR_svc

LR_abt

LR_irq

LR_und

PC

PC

PC

PC

PC

PC

CPSR

CPSR

CPSR

CPSR

CPSR

CPSR

SPSR_fiq

SPSR_svc

SPSR_abt

SPSR_irq

SPSR_und

Banked Registers

thumb state register set
Thumb State Register Set

System & User

FIQ

Supervisor

Abort

IRQ

Undefined

R0

R0

R0

R0

R0

R0

R1

R1

R1

R1

R1

R1

R2

R2

R2

R2

R2

R2

R3

R3

R3

R3

R3

R3

R4

R4

R4

R4

R4

R4

R5

R5

R5

R5

R5

R5

R6

R6

R6

R6

R6

R6

R7

R7

R7

R7

R7

R7

SP

SP_fiq

SP_svc

SP_abt

SP_irq

SP_und

LR

LR_fiq

LR_svc

LR_abt

LR_irq

LR_und

PC

PC

PC

PC

PC

PC

CPSR

CPSR

CPSR

CPSR

CPSR

CPSR

SPSR_fiq

SPSR_svc

SPSR_abt

SPSR_irq

SPSR_und

Banked Registers

state switching
State Switching

Thumb State

ARM State

R0

R0

R1

R1

R2

R2

R3

R3

R4

R4

R5

R5

R6

R6

R7

R7

R8

R9

R10

R11

R12

Stack Pointer (SP)

Stack Pointer (SP)

Link Register (LR)

Link Register (LR)

Program Counter (PC)

Program Counter (PC)

CPSR

CPSR

SPSR

SPSR

accessing r8 r12 in thumb state
Accessing R8..R12 in Thumb state
  • R8..R12 are not part of the standard Thumb register set.
  • There is limited access to R8..R12 in Thumb state, using special variants of the MOV instruction.
  • R8..R12 can be compared against or added to R0..R7 using CMP and ADD instructions
  • Conclusion:R8..R12 may have changed when switching back to ARM state.
the program status registers
The Program Status Registers
  • The ARM7TDMI contains a Current Program Status Register (CPSR), plus five Saved Program Status Registers (SPSR). These- hold Information about the most recently performed ALU operation- control the enabling and disabling of Interrupts- set the Processor operating mode

Condition Code

reserved

Control Bits

31

30

29

28

27

26

8

7

6

5

4

3

2

1

0

N

Z

C

V

.

.

.

I

F

T

M4

M3

M2

M1

M0

Overflow

Carry/Boorow

Zero

Negative

Mode

State

FIQ disable

IRQ disable

condition codes
Condition Codes
  • N, Z, C and V bits are the condition code flags.These may be changed as a result of arithmetic and logical operations and may be tested to determine whether an instruction should be executed.
  • In ARM state a l l instructions may be executed conditionally
  • In Thumb state, only the Branch instruction is capable of conditional execution
control bits
Control Bits
  • The T-bitReflects the operating state and is set when in Thumb
  • The Interrupt disable bitsAre used to mask (disable) the IRQ and FIQ interrupts
  • The mode bitsM4..M0 determine the operating mode. Not all combinations define a valid operating mode – Illegal values programmed into the mode bits will cause the processor enter an unrecoverable state. If this happens, a reset should be applied.
  • Reserved bitsShould never be altered.
exceptions 1
Exceptions (1)
  • Actions on entering an exception- Save return address in the appropriate LR Return address is either current PC + 4 or current PC +8 (depending on the exception)- Copy the CPSR into the appropriate SPSR- Force the CPSR mode bits to a value which depends on the exception- Load PC to fetch next instruction from the relevant exception vectorNote: If the processor is in Thumb state when an exception occurs, it will automatically switch into ARM state when the PC is loaded with the exception vector address.
arm state register set2
ARM State Register Set

System & User

FIQ

Supervisor

Abort

IRQ

Undefined

R0

R0

R0

R0

R0

R0

R1

R1

R1

R1

R1

R1

R2

R2

R2

R2

R2

R2

R3

R3

R3

R3

R3

R3

R4

R4

R4

R4

R4

R4

R5

R5

R5

R5

R5

R5

R6

R6

R6

R6

R6

R6

R7

R7

R7

R7

R7

R7

R8

R8_fiq

R8

R8

R8

R8

R9

R9_fiq

R9

R9

R9

R9

R10

R10_fiq

R10

R10

R10

R10

R11

R11_fiq

R11

R11

R11

R11

R12

R12_fiq

R12

R12

R12

R12

SP

SP_fiq

SP_svc

SP_abt

SP_irq

SP_und

LR

LR_fiq

LR_svc

LR_abt

Saved PC

LR_irq

LR_und

PC

PC

PC

PC

PC

PC

PC

PC

PC

CPSR

CPSR

CPSR

CPSR

CPSR

CPSR

CPSR

CPSR

CPSR

SPSR_fiq

SPSR_svc

SPSR_abt

SPSR_irq

Saved CPSR

SPSR_und

Banked Registers

exceptions 2
Exceptions (2)
  • Actions when leaving an exception- Load PC, minus an offset where appropriate, from LR (offset will vary depending on the exception)- Copy the SPSR back into the CPSRNote: An explicit switch back to Thumb state is not required, since restoring the CPSR from the SPSR automatically sets the T-bit to the value it held immediately prior to the exception.
exception vectors and priority
Exception Vectors and Priority

Note: Undefined Instruction and Software Interrupt are mutually exclusive,

since they each correspond to particular (non-overlapping) decodings

of the current instruction.

interrupt latencies
Interrupt Latencies

TD = Tsyncmax + Tldm + Tfiq

Tsyncmax is 5 clock cycles

Tldm is the time for the longest instruction to

complete (which is the LDM instruction)

and is 23 cycles

Tfiq is the time for the FIQ entry and is

2 clock cycles

@44 MHz this will give a total of 30 clocks

(less than 1us) for the processor to execute the FIQ

Instruction at address 0x1c.