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Long Shaping-time Silicon Readout

Long Shaping-time Silicon Readout. Bruce Schumm University of California, Santa Cruz Amsterdam ECFA-DESY Workshop April 1-4 2003. Participants. Dave Dorfan, Christian Flacco , Alex Grillo, Hartmut Sadrozinski, Bruce Schumm, Abe Seiden, Ned Spencer , Lan Zhang.

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Long Shaping-time Silicon Readout

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  1. Long Shaping-time Silicon Readout Bruce Schumm University of California, Santa Cruz Amsterdam ECFA-DESY Workshop April 1-4 2003

  2. Participants Dave Dorfan, Christian Flacco, Alex Grillo, Hartmut Sadrozinski, Bruce Schumm, Abe Seiden, Ned Spencer, Lan Zhang Also, a new post-doc (Gavin Nesom) will join the effort in April Potential external associates: SLAC, LPNHE Paris, CERN RD50

  3. North American SD Tracker

  4. Motivation - I Agilent 0.5 mm CMOS process (qualified by GLAST) Min-i for 300mm Si is about 24,000 electrons

  5. Motivation - II Use of long shaping-time read- out (low noise) plus exploitation of duty cycle permits development of very long, thin ladders Additionally, limited readout and servicing may lead to very limited material budget in forward region (down to 100 mrad)

  6. Scope and Funding Work funded via a two-year, $90,000 grant from the DOE Advanced Detector R&D Program (Will need to enter regular LC funding game afterwards) • 9 months graduate student support • Chip fabrication • Long-ladder development (existing sensors) • Electronics servicing to ladder

  7. Detailed Scope Given the duration and magnitude of the support, our `deliverables’ will be • Characterization of long shaping-time analog characteristics of CMOS process • Development of pulse development and electronic simulation for shaping-time and readout- scheme optimization • Demonstration of noise level commensurate with readout of 1-2m ladder • Demonstration of x100 suppression of IR heating loss • Min-i readout of long ladder

  8. Pulse Dev Simulation Effects incorporated: • Landau fluctuations (SS_SimSIdE, Jerry Lynch, LBNL) • Carrier (hole) diffusion / space-charge repulsion • Lorentz angle • Electronic noise • Pulse digitization / reconstruction

  9. Uncorrelated Sampling Check

  10. Long Shaping-time Bail-out Much of pulse simulation effort goes into `weighting- field’ calculation (pulse-development Green’s Fnc) However, integral of total charge is • e if electron hits strip • 0 if electron misses strip In t --> infinity limit, this is all you need to worry about!

  11. Carrier Diffusion Hole diffusion distribution given by Offest t0 reflects instantaneous expansion of hole cloud due to space-charge repulsion. Diffusion constant given by mh = hole mobility Reference: E. Belau et al., NIM 214, p253 (1983)

  12. Space-charge Effects Model deposition as uniform line of charge of radius b and linear charge density l. After separation of electrons, holes, distribution expands conformally:

  13. Time-Over-Threshold (TOT) TOT given by difference between two solutions to TOT/t (RC-CR shaper) q/r Digitize with granularity t/ndig

  14. Other Simulation Aspects For now, assume mobilizing field that of plane-biased diode (obscures details of field near strips) Lorentz Angle (holes): 36 mrad/T Variable inputs: • Detector geometry (pitch, thickness) • Magnetic field • Track parameters • Detector bias

  15. Result: S/N for 167cm Ladder At shaping time of 3ms; 0.5 mm process qualified by GLAST

  16. Pulse Simulation Goals Questions to be answered: • Signal-to-noise for long ladders • Optimal sensor geometry • Evaluation of analog readout scheme (time-over threshold; 2xTOT, direct analog, least-bit, etc.; goal of <7 mm resolution) • Effect of large magnetic fields • Effects of oblique angles of incidence • Optimal detector bias

  17. Hardware Qualification Leakage Current (A)

  18. Potential Associations Aurore Savoy-Navarro (LPNHE Paris) Have discussed development of full-scale ladder, readout for testbeam run RD-50 (CERN, Mara Bruzzi) Standing request for expert consultation (Lorentz angle, diffusion and mobility vs. B, etc.) Possible exploration of `Czochralski’ sensors (large area, but leakage current needs work for now)

  19. Next Six Months Immediately: begin SPICE-level optimization of shaping time (assuming 1-2 meter ladder) Have already begun qualifying GLAST 8-channel `cutoff’ structures for use in 2m ladder April: begin mechanical design and construction of two-meter ladder Submission of prototype ASIC in June-July

  20. Longer Term • Fall 2003: measure noise and power consumption characteristics • Winter 2003 (likely): begin design of 2nd prototype chip based on accumulated experience • Winter 2004: begin development of realistic prototype ladder, prepare for testbeam run • Summer 2004: testbeam studies; begin to develop scheme for back-end architecture NOTE: Project funded from DOE ADR program through 2003; afterwards, will need to switch to nominal sources!

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