A 12-bit high performance low cost pipeline ADC

1. A 12-bit high performance low cost pipeline ADC Le, H.P.; Zayegh, A.; Singh, J.; Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on Volume 2, 14-17 Dec. 2003 Page(s):471 - 474 Vol.2 指導教授：易昶霈 學　　生：吳柏翰 　學　　號：97662002 2008.10.13

2. Outline • Introduction • Sample-and-Hold Circuit • Noise Analysis • Conclusion 1

3. Introduction(1/3) • In this paper, a 12-bit high performance low cost pipeline ADC is presented. A modified flash ADC architecture has been employed to implement the pipeline coarse and fine ADCs instead of the traditional flash approach to reduce the device complexity and power consumption. 2

4. 3.14159… 3.14159… 0.14159… 3 011 3

5. 1 1 1 0 0 1 0 4

6. Sample-and-Hold Circuit(1/3) • system throughput and accuracy are limited by the speed and precision at which the input and residue analog voltages are sampled and hold. • The main advantages of this architecture is that the charge injection error and the clock feedthrough error are effectively removed. 5

7. Sample-and-Hold Circuit(2/3) SHC schematic diagram Unity-gain buffer 6

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9. Noise Analysis(1/3) • At 400MHz sampling frequency, noise analysis of the 12-bit pipeline ADC. • Noise analysis of Resistor, Coarse ADC, Inter-stage SHC, Sub-DAC and Inter-state Amplifier. 8

10. Inter-state Amplifier Inter-stage SHC Coarse ADC Sub-DAC 9

11. Noise Analysis(3/3) 10

12. Conclusion(1/2) 11

13. Conclusion(2/2) 12

14. The end.Thank you for your listen.