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VLSI Design

VLSI Design. Third Year Standard Project - SB1 Second Mini Lecture Web page: https://camtools.cam.ac.uk. David M Holburn David Chuah Jiming Jiang. 12th May - 6th June 2009. Summary of progress so far. Developed ring oscillator (RO) concept Confirmed using VHDL & ModelSim

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VLSI Design

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  1. VLSI Design Third Year Standard Project - SB1 Second Mini Lecture Web page: https://camtools.cam.ac.uk David M Holburn David ChuahJiming Jiang 12th May - 6th June 2009

  2. Summary of progress so far • Developed ring oscillator (RO) concept • Confirmed using VHDL & ModelSim • Explored effect of varying NOR delays (ModelSim) • Built symbol & schematic • Incorporated RO in Frequency Synthesiser design • Used Eldo to predict timing characteristics of RO using AMS NOR2 design • Investigated characteristics of real RO design using oscilloscope/counter

  3. Labs 5 & 6 Lab Guide 5 • Gain familiarity with layout and IC Station layout editor • Adaptmask layouts for the 2-input NOR gate nor2x • Identify/correct design rule violations in nor2 layout Lab Guide 6 • Verification - check for proper correspondence between your nor2x layout & the nor2x transistor schematic • Check transistor dimensions W & L • Investigate effect of parasitic elements C and R in layout • Simulate the gate’s characteristics with parasitics using Eldo

  4. The fabricated ring oscillator

  5. Layout and stick diagrams p and n-type MOSFETchannels MOSFET channels and interconnect Interconnect,channels and gate electrodes

  6. Layout and stick diagrams (2) Input Contact cuts(one of four) Output

  7. Form Factor Identical logic functions Channels aligned horizontallyShort, wide form factor Channels aligned verticallyTall, thin form factor

  8. VDD D D S S VSS Stick diagrams: NAND Input A Output Input B

  9. Output in polySicrosses under VDD VDD VSS Stick diagrams: NOR Input B NB: contact cutlinks m1 and poly Output wired in metal 1 Input A

  10. Design rules Mask : Poly1 4A Minimum poly1 width 0.35m Current density must not exceed 500A/m 4C Minimum Poly1 spacing or notch width 0.45 m 4D Minimum Poly1 to Diffusion spacing 0.20 m 4B Minimum Gate length (0.35 m) 4E Minimum Poly1 extension on field oxide 0.40 m 4F Minimum source and drain width 0.50 m

  11. Lab Guide 5 - layout of nor2x • IC Station operations • familiarise with basic techniques • study & understand layout • detect & correct rule violations • add gate electrodes • connect output • consider how to optimise layout • size • speed • convenience of input/output • compatible with other cells • plot completed layout

  12. Eldo - for detailed simulation

  13. DC characteristic for nor2x

  14. Transient performance of nor2x

  15. Parasitic capacitances in nor2t

  16. Capacitances due to interconnect

  17. Wiring parasitics

  18. Response with all parasitics

  19. Final week – Complete System Lab Guide 7 • Use Design Architect-IC to create top-level schematic • Incorporates all design blocks • Programmable divider and its sub-blocks • Ring Oscillator • Single NOR gate • Input/Output and Power pads • Simulate entire system using Eldo • May take several minutes to run!

  20. Final week - Semi Custom Design Lab Guide 8 • Use IC Station, ICassemble & ICBlocks • Create complete IC layout for synthesiser module • Automatic and interactive floor-planning • Automatic cell placement • Automatic routing of interconnect • Flattened and Hierarchical designs • Generate colour check plot of result • Your design is complete!

  21. Hierarchical layout design • Hierarchy - a methodology for creating larger design from smaller design objects • At lowest level objects are polygons, shapes and paths (leaf cells), e.g. nor2, nand2 • Inserted in a multi-tiered, hierarchical design • Designer controls visibility of detail • Allows construction of libraries of commonly used parts e.g. divider (based on count4) • Permits re-use of designs in other projects

  22. Hierarchical Objects comparator divider ring_oscillator control single_nor

  23. Example schematic for counter

  24. Floor plan for counter

  25. Place & Route standard cells All nets shown yellow are routed right away - unrouted nets in green

  26. Example ring_oscillator schematic

  27. Floorplan for ring_oscillator

  28. Place & Route for ring_oscillator

  29. Layout for Core (all blocks)

  30. Top-level layout with I/O & power

  31. Completed layout

  32. Completed layout

  33. Completed layout

  34. Completed layout

  35. The End - 2009

  36. After compaction

  37. Flattened layout top_level_flat

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