slide1 n.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
Inter strip resistance in silicon position-sensitive detectors PowerPoint Presentation
Download Presentation
Inter strip resistance in silicon position-sensitive detectors

Loading in 2 Seconds...

play fullscreen
1 / 19

Inter strip resistance in silicon position-sensitive detectors - PowerPoint PPT Presentation


  • 106 Views
  • Uploaded on

Inter strip resistance in silicon position-sensitive detectors. E. Verbitskaya , V. Eremin, N. Safonova* Ioffe Physical-Technical Institute of Russian Academy of Sciences St. Petersburg, Russia *also Saint-Petersburg Electrotechnical University “LETI”, Russia N. Egorov, S. Golubkov

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about 'Inter strip resistance in silicon position-sensitive detectors' - judah-santana


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
slide1

Interstrip resistance

in silicon position-sensitive detectors

E. Verbitskaya, V. Eremin, N. Safonova*

Ioffe Physical-Technical Institute of Russian Academy of Sciences

St. Petersburg, Russia

*also Saint-Petersburg Electrotechnical University “LETI”, Russia

N. Egorov, S. Golubkov

Research Institute of Material Science and Technology (RIMST)

Zelenograd, Russia

15 RD50 Workshop

CERN, Geneva, November 16-18, 2009

slide2

Outline

  • Motivation
  • Physical model of interstrip resistance
  • Experimental results on interstrip resistance in as-processed Si detectors
  • Influence of nonequilibrium carrier generation
  • RISin n-type FZ and CZ Si samples
  • Conclusions

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

slide3

Motivation

Current subjects:

 Development of operational model for voltage terminating structure (VTS) and current terminating structure (CTS, edgeless detectors)

 Strip detector performance at SLHC: very high fluences and enhanced bulk generated current

 Noise performance of spectroscopic strip detectors (GSI, Darmstadt)

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

slide4

1

2

Special design of test structures

p+-n-n+ structure

- area 1x1 mm2

Strips:

two interpenetrating “combs”:

- pitch 25 mm

 increased length

of interstrip gap

 equivalent to 4 cm strips

FZ n-Si, r>5 kW

d = 300 mm Vfd  20 V

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

slide5

Physical model

j1 = j2

- potentials at the strips

  • Components that control
  • interstrip resistance RIS:
  • surface leakage
  • interface current

Distortion of symmetric distributions of potential and electric field

may stimulate excess current flow between strips

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

slide6

Measurements

of interstrip gap characteristics

U1 – bias voltage

applied to p-n junction

U2– bias voltage

between the strips

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

slide7

I-V characteristics of interstrip gap

FZ n-Si, # WP 3-6-2

I = Id + Iinst

Id – strip dark current

Iinst – interstrip current

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

slide8

DU2cr

hole drift

Current flow in interstrip gap

DU2cr - range of bias voltage

in which Iinst is small

 DU2cr  with U1

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

slide9

Interstrip current Iinst

Iinst(U2): dark current is subtracted

Interstrip resistance:

RIS = dU2/dIinst

Regions with different slopes:

A and A*:

RW = (dIinst/dU2)-1

- ohmic isolation resistance, independent on U1, related mainly with surface leakage

B: current step dIinst

dIinstand dIinst/dU2

as U1

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

slide10

Origin of interstrip current step dIinst

j1≠ j2

  • Current switching –
  • redistribution of strip hole
  • currents
  • In detector:
  • Switching acts as
  • negative feedback
  • recovery of potential

balance

Rsw = (dIinst/dU2)-1

in dIinst region

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

slide11

Interstrip resistance vs bias voltage

RW 200 GW

irrespective to U1 and at ±U2

Rsw = dU2/dIis at U2 0

Rsw  with U1

RW > Rsw

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

slide12

Influence of nonequilibrium carrier generation

Carrier generation:

- by LED illuminating p+ side

- white light on n+ side

I = Iph + Iinst

E. Verbitskaya et al., 15 RD50 Workshop,

CERN, Geneva , Nov 16-18, 2009

slide13

Influence of nonequilibrium carrier generation on RIS

  • RW and Rsw

with carrier generation

RW: p+ illumination

– high n and p under SiO2

  • Rsw at carrier generation:

no dependence on U1

– switching iscontrolled

by photocurrent

rather than dark current

Ratio of Rswis about one half of current ratio

since ½ of a total structure current is switched

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

slide14

Influence of Si type

FZ n-Si

CZ n-Si

Similar behavior of Iinst vs. U1 and U2

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

slide15

Comparison of Iinst for different Si types

DU2cris smaller in CZ Si

dU2corresponding to dIinst is smaller in CZ Si

RWis similar

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

slide16

Comparison of Rsw for different Si types

Rsw is smaller in CZ Si

Parameterization: Rsw = A - B(U1)0.5

FZ: Rsw= 7.21010 – 5.9 109(U1)0.5

CZ: Rsw= 2.51010 – 2.2109(U1)0.5

Rsw depends on bulk generation current

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

slide17

Future studies

  •  Different wafer orientation

 Detectors with different configuration

  •  Study of irradiated Si detectors

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

slide18

Conclusions

The factors that define interstrip isolation resistance are:

- surface leakage,

- interface current,

- new mechanism - distortion of symmetric potential distribution at the strips and switching of strip currents.

 Switching of strip currents is a negative effect since it decreases interstrip isolation. This effect may control interstrip resistance rather than ohmic conductance between the strips.

RWis about 200 GWirrespective to the bias voltage

while Rsw is bias dependent and decreases with bias voltage rise down to few GW.

Results are partially published in:

V. Eremin et al., Semiconductors43(2009) 796.

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009

slide19

Acknowledgments

  • This work was made in the framework of RD50 collaboration
  • and supported in part by:
  • RF President Grant # 2951.2008.2
  • Fundamental Program of Russian Academy of Sciences
  • on collaboration with CERN

Thank you for attention!

E. Verbitskaya et al., 15 RD50 Workshop, CERN, Geneva , Nov 16-18, 2009