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Motivation Experimental conditions

Characterization of irradiated MOS-C with X-rays using CV-measurements and gated diode techniques Q. Wei, L. Andricek, H-G. Moser, R. H. Richter, Max-Planck-Institute for Physics Semiconductor Laboratory. Outline. Motivation Experimental conditions

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Motivation Experimental conditions

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  1. Characterization of irradiated MOS-C with X-rays using CV-measurements and gated diode techniquesQ. Wei, L. Andricek, H-G. Moser,R. H. Richter, Max-Planck-Institute for Physics Semiconductor Laboratory

  2. Outline • Motivation • Experimental conditions • Study of the radiation damage by CV-measurements and gated diode technique, annealing behavior at RT, comparison of extracted Nox, Nit values • Discussion of the results

  3. Motivation • Radiation damage of semiconductor devices (e.g. DEPFET) • Study on the radiation damage with MOS-C using CaliFa teststand at MPI HLL Munich • Comparison of results from two different measurement methods (MOS-C and gated diode)

  4. t 0 Comparison between different semiconductor devices (Only for the 1-D defects)

  5. Experimental Conditions • Irradiation: X-Ray tube with Mo target at 30kV and 30mA (17,44keV & Bremsstrahlung ) dose: 1 week of irradiation up to 1M rad, dose rate: 2.5rad/s (1rad=0.01J/kg) • Samples: • Based on n-type high resistance silicon(450mm) wafer: doping concentraion ~ 1012 cm-3 • Bias conditions: +5V,0V,-5V for MOS-C; 0V for gated diode • Measurements: • CV: HF (10kHz); LF (20Hz) all values in series mode (Cs, Rs) • Gated diode: VAl: 10V, Vedge: 0.25V, VAl/Poly: from positive to negative values • Annealing: at RT for about 5 days on MOS-C and 10 days on Gated Diode

  6. Cross section and layout of MOS-C • MOS-C: • the upper left – Al1 • the upper right – Al2 • the lower left –Poly1 • the lower right –Poly2 • each contact area is about 10 mm2 Al2 Al Poly1/2 Aluminium Poly1/Poly2 LTO Substrate Substrate Oxide Ni

  7. extracted results forMOS-C & Gated Diode Gate Bias conditions: 0V For MOS-C CV-Measurement

  8. Gate Bias conditions: 0V For MOS-C CV-Measurement high-low frequency CV  Nit Flat band voltage Shift Nox

  9. Gate bias conditions: 0V Weak annealing Annealing for MOS-C (~25%) During annealing Nox decreases linearly with ln(t) (~6,5%) (~6,5%)

  10. For MOS-C Gate bias conditions: +5V Due to too large leakage current at dose 200krad CV-Measurement does not work literatur: Interface trap will not saturate at dose of 1Mrad!

  11. For MOS-C Gate bias conditions: -5V

  12. For MOS-C VG at +5V Vs. VG at 0V Much more defects (Nox,Nit)for positive gate than for 0V bias both poly-gate and Al-gate structure VG at -5V Vs. VG at 0V Almost the same amount of defects (Nox,Nit)for negative gate bias as for 0V both poly-gate and Al-gate structure For any given VG More defectsfor Al-gate than poly-gate

  13. Erde V V Al/PolyGate A Al Edge Substrate P+ N 95µm 5µm Cross section structure and layout for gated diode • gated diode wafer • the left one – Al • the right one –poly • each area is 9 mm2 Poly-gate Al-gate Al Al P+ P+ grounding Edge

  14. Gate bias conditions: 0V For gated Diode By using gated diode technique ? peak shift  Nox Full width at 2/3 Imax Nit

  15. Gate bias conditions: 0V For gated Diode Using CV-method (HF) A good agreement for determination of Nox by ΔVFB(CV) and ΔVG(gated diode technique)

  16. Using gate controlled diode technique Gate bias conditions: 0V Annealing for Gated Diode Small fraction of positive oxide charges (~11%) are recoverd! Weak annealing During annealing Nox decreases linearly with ln(t)

  17. for Gated Diode Gate bias conditions: 0V (due to another traps)

  18. "ON" "OFF" Results for DEPFET Bias during irradiaton: 1: empty int. gate, in „off“ state, VGS= 5V, VDrain=-5V  Eox ≈ 0 2: empty int. gate, in „on“ state, VGS=-5V, VDrain=-5V  Eox ≈ -250kV/cm 3: all terminals at 0V No annealing during irradiation  ~ 3 days irradiation GSF – National Research Center for Environment and Health, Munich 60Co (1.17 MeV and 1.33 MeV) Radiation Effects (ionizing radiation) • postive oxide charge: negative shift of the theshold voltage (~tox2) • interface traps: higher 1/f noise and reduced mobility (gm)

  19. s=85mV/dec Vth=-0.2V s=155mV/dec Vth=-4.5V Transconductance and subtreshold slope No change in the transconductance gm 300 krad  Nit≈2·1011 cm-2 912 krad  Nit≈7·1011 cm-2 Literature: After 1Mrad 200 nm (SiO2): Nit ≈ 1013 cm-2

  20. Discussion of the results Comparison of Nox and Nit between MOS-C and gated diode for Al- and poly-gate structure at dose of 189krad and 1Mrad ≈ ≈ ≈ For poly-gate structure: more Nit on Gated diode than on MOS-C For Al-gate structure: more Nit and Nox on MOS-C than on Gated diode For Nox: the same for both Al-gate and poly-gate structure (Gated diode) For Nox: More Nit for poly-gate than Al-gate structure (Gated diode) More Nit and Nox for Al-gate than poly-gate structure (MOS-C) For Nox: a good agreement for poly-gate structure (MOS-C & gated diode) (Poly-gate structure for three devices) ≈ For Nox: DEPFET=Gated diodeMOS-C √ For Nit: DEPFET>Gated diode>MOS-C ?

  21. Comparison between literature and our experiment • Differences for the saturation effect of interface trap on MOS-C • Differences for the generation of defects on MOS-C (poly-gate for DEPFET) • Differences for defect generation at negative gate bias on MOS-C Winokur, 1985. Derbenwick, Gregory, 1975 T.P. Ma, P. Dressendorfer John Wiley&Sons,1989.

  22. Backup slides

  23. 55Fe Counts/channel Energy (eV) Performance before irradiation • non-irrad. double pixel DEPFET • L=7μm, W=25 μm • Vthresh≈-0.2V, Vgate=-1V • Idrain=41 μA • Drain current read out • time cont. shaping =6 μs Noise ENC=2.3 e- (rms) at T>23 degC

  24. Performance after irradiation for DEPFET • Irradiated double pixel DEPFET • L=7μm, W=25 μm • after 913 krad, 60Co • Vthresh≈-4V, Vgate=-5.3V • Idrain=21 μA • Drain current read out • time cont. shaping =6 μs 55Fe Counts/channel Noise ENC=7.9 e- (rms) at T>23 degC Energy (eV) Non-irradiated: Noise ENC=2.3 e- (rms)

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