Mobile System Considerations for SDRAM Interface Trends

1. Mobile System Considerations for SDRAM Interface Trends Andrew B. Kahng†‡, Vaishnav Srinivas‡¥ June 5th, 2011 CSE† and ECE‡ Departments University of California, San Diego Qualcomm Inc. ¥

2. Outline • SDRAM Memory Interfaces: Today and Tomorrow • Motivation • Trends in DRAM Density and Data Rate • Trends in Mobile Processor Requirements • Memory Interface Calculator • Exploration Using the Calculator • Summary and Next Steps

3. SDRAM Memory Interfaces Today and Tomorrow • Various interconnect and signaling options exist: • Interconnect: Die stack/MCP POP DIMM 3D-Stack • Signaling: DDR, XDR, Serial, Wide IO • Exploration of these options based on the primary bounds (Capacity, Throughput, Power and Latency) is required for making the correct tradeoffs

4. Motivation • The memory interface calculator includes: • IO switching, bias and termination power • IO/PHY and interconnect latencies • Input parameters for exploration: • Termination values • Loading • Number of data and strobe pins • Memory timing parameters • IO/PHY “retiming” power • Predict gaps between offerings and requirements • Integrating into CACTI can help exploration of system metrics

5. Trends in DRAM Capabilities • DRAM densities to double every 3 years • Projections for DRAM densities revised downwards over time • Current densities at 4Gb/die • DRAM data rates to double every 4-5 years • Projections for DRAM data rates revised upwards over time • Current data-rates at 2.2 Gb/s

6. Trends in Mobile Processor Requirements • Trends for mobile processor requirements • Capacity to scale 3-4x every 3 years • Throughput to double every 3 years • The requirements are very dynamic! • Quick exploration and projection for compatible memories is useful Capacity Requirements in GB (Source: IDC) Mobile Handset Throughput Requirements in GB/s (Source: Qualcomm)

7. Memory Interface Calculator

8. Memory Interface Calculator Summary

9. Memory Interface Calculator Summary • The spider chart highlights the design space covered • Wide IO covers the largest space for lower capacities • Large capacity systems still need DDR3/DDR4 • Alternatives to be explored outside the existing space? • Before LPDDR3 came up in JEDEC, Wide-IO and Serial Memory were being explored. • LPDDR3 was brought up as a way to fill this gap in 2012-2014 timeframe Throughput in GB/s

10. Exploration using the calculator • How fast can LPDDR3 operate? • With terminations? • With DLL/better retiming? • With lower loading? • With better packaging? • POP versus MCP • Wide IO exploration? • Transition to DDR for Wide IO? • Number of data lanes per strobe – 8, 16 or 32? • When does interface timing and signal/power integrity become an issue for Wide IO? • High-capacity memory alternatives to DDR3/DDR4? • MCP with larger number of wire-bonded dies? • TSS with large number of stacks (8?) • TSS-MCP if stacking with processor is a thermal risk?

11. LPDDR3 Exploration

12. LPDDR3 Exploration

13. Summary and Next Steps • A simple framework to model interconnect and IO/PHY timing and power for existing and upcoming SDRAM memory interfaces • Helps explore standards and design space • Helps identify gaps between DRAM and SOCs • Next Steps: • Integrate the memory interface models within CACTI • Challenge the calculator for future usage cases for mobile products • Include more parameters, including silicon area, packaging options and number of data lanes per strobe pin