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DDR SDRAM Memory Interface

DDR SDRAM Memory Interface. Agenda. Why DDR? DDR vs. SDR Understanding DDR SDRAM Bus timing CoolRunner-II and DDR SDRAM demo board CoolRunner-II DDR SDRAM design. Why DDR?. DDR = Double Data Rate Provides ability to read or write two pieces of information in each clock cycle

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DDR SDRAM Memory Interface

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  1. DDR SDRAM Memory Interface

  2. Agenda • Why DDR? • DDR vs. SDR • Understanding DDR SDRAM • Bus timing • CoolRunner-II and DDR SDRAM demo board • CoolRunner-II DDR SDRAM design

  3. Why DDR? • DDR = Double Data Rate • Provides ability to read or write two pieces of information in each clock cycle • Doubles the bandwidth of the device without increasing the clock speed or bus width

  4. DDR vs. SDR Functionality • Memory core of DDR and SDR are the same • Addressing scheme • Command control interface • Memory bank array structure • Refresh requirements • The main difference is in the data interface: • SDR is fully synchronous (posedge of clk) • DDR is true source-synchronous meaning data is captured twice per clock cycle, with a bi-directional data strobe (DQS)

  5. Strobe-Based Data Bus • To allow for higher data rates, data strobe signals were added to DDR devices: • DDR data strobes (DQS) are non-free-running signals that are driven by the device which is driving the data signals • Controller drives DQS for WRITE operations • DDR SDRAM drives DQS for READ operations

  6. DDR Enhancements • DDR utilizes a differential pair for the system clock (CLK and CLK#) • Data is transmitted on both positive and negative edges of the clock • DDR devices incorporate an on-chip delay locked loop (DLL) • Data strobes are added to improve data capture reliability • SSTL_2 signaling techniques are used • DDR utilizes a 2n-prefetch architecture • Internal data bus is twice the size of external data bus

  7. Parameter SDR DDR DQM Yes No DM (Data Mask) No Yes DQS (Data Strobe) No Yes CK# (System Clock) No Yes Vref No Yes VDD and VDDQ 3.3V 2.5V Signal Interface LVTTL SSTL_2 Data Rate 1x Clock 2x Clock Architecture Synchronous Source-Synchronous SDR vs. DDR Summary

  8. CoolRunner-II DDR SDRAM Evaluation Board

  9. 2.5 V VREF Out Micro Linear ML6554 Bus Terminator LP3964 1.8 V VTT Out LP3964 Micron 128 Mb DDR MT46V16M8 Xilinx CR-IIXC2C256 CLK CR-II / DDR Demo Board VTT & VREF Generation 2.5V/1.8V Regulator CR-II & DDR SDRAM

  10. VTT VTT RT RT RS RS + ZO = 50 Ohm - VREF VTT RT RS + ZO = 50 Ohm - VREF SSTL_2 Termination

  11. ZO = 50 Ohm CR-II / DDR Termination VTT VTT VTT 128 Mb DDR SDRAM ZO = 50 Ohm VREF

  12. CPLD Design • DDR SDRAM controller design fits into a XC2C256 (~50% utilization for DDR) • Includes the following: • Initialization state machine • DDR controller • Refresh logic • Test read/write logic (LFSR) • Board interface

  13. CPLD Block Diagram 12 8-bit LFSR ddr_a Refresh Logic 2 ddr_ba 8 ddr_dq rfsh_flag DDR Controller State Machine ddr_dqs int_cmd ddr_cke Initialization / Test Logic State Machine ddr_cs int_data ddr_ras int_addr ddr_cas ddr_we ddr_clk ddr_clkn Board Logic

  14. NOP Deselect DDR SDRAM. No new commands executed. LOAD MODE REGISTER Defines operating mode of SDRAM. ACTIVE Opens row in specified bank for access. READ Initiates burst read operation. WRITE Initiates burst write operation. BURST TERMINATE Terminates a burst read. PRECHARGE Deactivates open row in specified bank. AUTO REFRESH Retains data in SDRAM. DDR Commands

  15. SDRAM Addressing • 23-bit system address bus = 128 MB memory • SDRAM data is organized into banks • Each bit location is specified with a row and column address BankAddress Row Address Column Address 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Load Mode Register Data

  16. Wait for stable power & clock inputs Wait 200 Clock Cycles NOP Precharge All Addresses Precharge All Addresses Execute 2 Auto Refresh Commands Extended Mode Register Write (Enable DLL) Mode Register Write (Reset DLL) Mode Register Write (Set CAS & burst) Initialization Sequence

  17. cmd = AUTO_REFRESH cmd = PRECHARGE PRECHARGE AUTO_RFS IDLE cmd = LOAD MR cmd = READ or WRITE LOAD_MR ACTIVE WRITE READ BRST_TERM cnt < CAS_LAT cnt < BURST_LEN WR_DATA CAS_LAT cmd = BURST_TERM RD_DATA cnt < BURST_LEN Controller State Machine

  18. DDR Clock Requirements

  19. Vcc T ddr_clk Q sys_clk 2.5V OUT OBUF 3.3V IN GCK RST Vcc T ddr_clkn Q sys_clk 2.5V OUT OBUF 3.3V IN GCK PRE DDR Clock Generation

  20. DDR Clock Timing T = 7.5 ns sys_clk tCO = 5 ns ddr_clk ddr_clkn T = 15 ns 7.5 ns DDR Clock Period 15 ns (133 MHz) (66.67 MHz)

  21. DDR Clock Generation (TCO) sys_clk ddr_clk ddr_clkn

  22. DDR Clock Generation (VMP) sys_clk ddr_clk ddr_clkn

  23. Bank/Row Activation • Prior to a READ/WRITE operation the specific bank/row must be activated

  24. Typical Write Burst • DQS generated by CPLD • DQS must be center aligned with DQ

  25. Typical Read Burst • DQS is edge aligned to DQ • Read interrupted with BURST TERMINATE command

  26. Data Valid Read Window sys_clk ddr_clk ddr_clkn ddr_dq D1 D0 ddr_dqs DVW DVW CPLD captures data DVW = tCK/2 - tAC(max) + tAC(min) = 7.5 ns - (0.75 ns) + (-0.75 ns) = 6 ns

  27. Data Valid Window ddr_dqs ddr_dq(0) ddr_dq(1) ddr_dq(2)

  28. Read & Write (Burst 2) ddr_clk ddr_dqs ddr_dq(0) ddr_dq(1)

  29. Read & Write (Burst 4) ddr_clkn ddr_clk ddr_dqs ddr_dq(0)

  30. Read & Write (Burst 8) ddr_clkn ddr_clk ddr_dqs ddr_dq(0)

  31. Precharge Operation • Precharge deactivates the open row in a particular bank or all banks • After a precharge, the specific row address must be activated with an ACTIVE command prior to use • Auto PRECHARGE : A10 specifies precharge after current READ/WRITE operation • Self PRECHARGE: separate command (must wait tRP)

  32. Refresh Requirements • Refresh is required at intervals of 15.625 µs • Only one refresh command is required • Option to issue up to 8 refresh commands every 140.6 µs

  33. DDR SDRAM Vendors • Memory vendors providing DDR SDRAM: • Micron, Infineon, Cypress, Samsung, Hitachi, Fujitsu, Hyundai, IDT, Mitsubishi, SiberCore, Toshiba...

  34. Conclusion • Reference board works up to 100 MHz on DDR SDRAM • Current DDR design can be modified for SDR SDRAM applications • Check out application note XAPP384 on DDR & CoolRunner-II reference design

  35. Demo Slides

  36. Demo Burst = 2 8-bit LFSR Test Control Logic 8 8 Upper Byte int_data[15:0] Lower Byte DDR Control Logic ddr_dq[7:0]

  37. Demo Data read from DDR Data wrote to DDR MSB … LSB MSB … LSB

  38. Appendix

  39. DQM (SDR only) Internal Data Bus Col0 (DDR only) SDRAM Core

  40. SDR Interface

  41. DDR Interface Col0

  42. SSTL_2 Signaling

  43. DDR Write Logic 8-bit LFSR int_data (TEST SM Logic) D lfsr_clk (TEST SM Logic) Q ddr_dq[7:0] T Q ddr_clk DualEdge DDR SM Logic D ddr_write_en Q ddr_clk ddr_dqs_t T ddr_dqs Q ddr_clk DualEdge

  44. DDR Read Logic DDR SM Logic ddr_read_en T Q ddr_clk DualEdge ddr_dqs CE ddr_dq[7:0] D int_data_rd[15:8] Q sys_clk LED Board Logic ddr_dqs CE ddr_dq[7:0] D int_data_rd[7:0] Q sys_clk

  45. CLK/CLK# Generation

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