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Chapter 6. Functions of Combinational Logic. Adder. Figure 6--1 Logic symbol for a half-adder. Figure 6--2 Half-adder logic diagram. Figure 6--3 Logic symbol for a full-adder. Figure 6--4 Full-adder logic. Figure 6--5 Full-adder implemented with half-adders.

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chapter 6

Chapter 6

Functions of Combinational Logic

figure 6 13 two 74ls83a adders connected as an 8 bit parallel adder pin numbers are in parentheses
Figure 6--13 Two 74LS83A adders connected as an 8-bit parallel adder (pin numbers are in parentheses).
slide20
Figure 6--20 Pin diagram and logic symbol for the 74HC85 4-bit magnitude comparator (pin numbers are in parentheses).
figure 6 32 examples of zero suppression using the 74ls47 bcd to 7 segment decoder driver
Figure 6--32 Examples of zero suppression using the 74LS47 BCD to 7-segment decoder/driver.
slide33

Figure 6--34 Basic logic diagram of a decimal-to-BCD encoder. A 0-digit input is not needed because the BCD outputs are all LOW when there are no HIGH inputs.

slide34

Figure 6--35 Pin diagram and logic symbol for the 74HC147 decimal-to-BCD priority encoder (HPRI means highest value input has priority).

slide38

Code Converter

BCD-to-Binary Conversion

slide46
Figure 6--45 Pin diagram and logic symbol for the 74HC157A quadruple 2-input data selector/multiplexer.