6.5.8 Equivalent circuit for the MOSFET
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6.5.8 Equivalent circuit for the MOSFET - PowerPoint PPT Presentation

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6.5.8 Equivalent circuit for the MOSFET. Parasitic elements in the MOSFET equivalent circuit. Capacitance The gate capacitance C i is the sum of the distributed capacitance from the gate to the source end of the channel (C GS ) and the drain end (C GD ).

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Parasitic elements in the MOSFET equivalent circuit

  • Capacitance

  • The gate capacitance Ci is the sum of the distributed capacitance from the gate to the source end of the channel (CGS) and the drain end (CGD).

  • The overlap capacitance from the gate-to-source (COS) and gate-to-drain (COD).

    • COD is also known as Miller overlap capacitance.

  • The p-n junction depletion capacitances associated with the source (CJS) and drain (CJD).

  • Resistance

  • The source/drain series resistances (RS and RD).

  • The resistances in the substrate between the bulk contact and the source and drain (RBS and RBD).

  • Current source

  • The drain current can be modeled as a (gate) voltage-controlled constant current source.

Miller overlap capacitance

  • The Miller overlap capacitance (GOD) is particularly problematic because it represents a feedback path between the output drain terminal and the input gate terminal.

  • One can measure the Miller capacitance at high frequency by holding the gate at ground (VG=0) so that an inversion layer is not formed in the channel.

  • Thereby, most of the measured capacitance between gate and drain is due to the Miller capacitance, rather than the gate capacitance Ci.

  • Minimization of Miller capacitance by self-aligned gate.

    • Gate itself is used to mask the source/drain implants, thereby achieving alignment.

  • There is always certain amount of overlap.

    • Lateral straggle or spread of the implanted dopants underneath the gate.

    • Further spread by lateral diffusion during high temperature annealing.

Reduced channel dimension of L and Z

  • L

  • The spread of the source/drain junctions under the gate edge determines what is called the channel length reduction, LR.

  • The electrical or “effective” channel length, Leff, in terms of the physical gate length, L as Leff = L -LR.

  • Z

  • The width reduction results from the physical isolation regions that are formed around all transistors, generated by LOCOS.

Source/drain series resistance

  • Source/drain series resistance RSD = (RS + RD).

  • It degrades the drain current and transconductance.

    • For a certain applied drain bias to the source/drain terminals, part of the applied voltage is “wasted” as an ohmic voltage drop across these resistance, depending on the drain current (or gate bias).

      • The actual drain voltage applied to the intrinsic MOSFET itself is less.

      • Causes ID to increase sub-linearly with VG.

Determination of RSD and LR

  • In the linear region

  • We can measure VD/ID in the linear range for various MOSFETs having the same width, but different channel lengths, as a function of substrate bias.

  • Varying the substrate bias changes the VT through the body effect, and therefore the slope of the straight lines that result from plotting the overall resistance as a function of L.

  • The lines pass through a point, having values which correspond to RSD and LR.

Determination of RSD and LR

Dimensional scaling of MOSFET

  • Scaling improves packing density, speed, and power dissipation.

 (voltage scaled accordingly to keep the internal electric fields more or less constant)

  • Various structural parameters of the MOSFET should be scaled in concert if the device is to keep functioning properly. (by Dennard at IBM)

  • Scaling of depletion widths is achieved indirectly by scaling up doping concentrations.

Problem of scaling

  • The internal electric fields in the device would increase if the power supply voltages are kept the same.

  • The longitudinal electric fields in the pinch-off region, and the transverse electric fields across the gate oxide, increase with MOSFET scaling.

  • Problems known as hot electron effects and short channel effects.

Hot electron effects

  • When an electron travels from the source to the drain along the channel, it gains kinetic energy at the expense of electrostatic potential energy in the pinch-off region, and becomes a “hot” electron.

  • A few of the electrons can become energetic enough to surmount the 3.1 eV potential barrier between the Si channel and the gate oxide.

    • Some of the injected hot electrons can go through the gate oxide and be collected as gate current, thereby reducing the input impedance.

    • Some of these electrons can be trapped in the gate oxide as fixed charges.

      • This increases the flat band voltage and therefore the VT.

    • These energetic hot carriers can rupture Si-H bonds that exist at the Si-SiO2 interface, creating fast interface states that degrade MOSFET parameters such as transconductance and subthreshold slope.

      • The increase of VT and decrease of slope, and therefore transconductance.

Lightly doped drain (LDD)

  • The solution to hot electron effect is to use what is known as lightly doped drain (LDD).

  • By reducing the doping concentration in the source/drain, the depletion width at the reverse-biased drain-channel junction is increased and the electric field is reduced.

  • Hot carrier effects are less problematic for holes in p-channel MOSFETs than for electrons in n-channel devices for two reasons.

    • The channel mobility of holes is approximately half that of electrons; hence, for the same electric field, there are fewer hot holes than hot electrons.

      • Unfortunately, the lower hole mobility is also responsible for lower drive currents in p-channel than in n-channel.

    • The barrier for hole injection in the valance band between Si and SiO2 is higher (5 eV) than for electrons in the conductance band (3.1 eV).

      • Hence, while LDD is mandatory for n-channel, it is often not used for p-channel devices.

“Signature” of hot electron effect

  • As the electrons travel towards the drain and become hot, they can create secondary electron-hole pairs by impact ionization.

  • The secondary electrons are collected at the drain, and cause the drain current in saturation to increase with drain bias at high voltages, thereby leading to a decrease of the output impedance.

  • The secondary holes are collected at the substrate as substrate current.

    • This current can create circuit problems such as noise or latchup in CMOS circuit. (9.3.1)

    • It can be used as a monitor for hot electron effects.

  • Signature

  • Substrate current initially increases with gate bias (for a fixed, high drain bias), goes through a peak and then decreases.

  • Initially, as the gate bias increases, the drain current increases and thereby provides more primary carriers into the pinch-off region for impact ionization.

  • However, for even higher gate bias, the MOSFET goes from the saturation region into the linear region when the fixed VD drops below VD(sat.) = (VG – VT).

  • The longitudinal electric field in the pinch-off region drops, thereby reducing the impact ionization rates.

Short channel effect 1: Drain-induced barrier lowering

  • If small channel length MOSFETs are not scaled properly, and the source/drain junctions are too deep or the channel doping is too low, there can be unintended electrostatic interactions between the source and the drain known as Drain-Induced Barrier Lowering (DIBL).

  • As the drain bias is increased, the conduction band edge in the drain is pulled down, and the drain-channel depletion width expands.

    • For a long channel MOSFET, unless the gate bias is increased to lower this potential barrier, there is little drain current.

    • For a short channel MOSFET, as the drain bias is raised and the conduction band edge in the drain is pulled down, the source-channel potential barrier is lowered due to DIBL.

  • The problem can be mitigated by applying a substrate reverse bias, because that raises the potential barrier at the source end.

    • The onset of DIBL is sometimes considered to correspond to the drain depletion region expanding and merging with the source depletion region.

    • However, DIBL is ultimately caused by the lowering of the source-junction potential barrier below the built-in potential.

    • This works in spite of the fact that the drain depletion region interacts even more with the source depletion region under such back bias.

    • Once the source-channel barrier is lowered by DIBL, there can be significant drain leakage current, with the gate being unable to shut it off.

Solutions to DIBL

  • The source/drain junctions must be made sufficiently shallow (i.e., scaled properly) as the channel lengths are reduced, to prevent DIBL.

  • The channel doping must be made sufficiently high to prevent the drain from being able to control the source junction.

    • Achieved by performing anti-punch-through implant in the channel.

    • Sometimes, instead of such an implant throughout the channel, a localized implant is done only near the source/drains. Known as halo or pocket implants.

      • The higher doping reduces the source/drain depletion widths and prevents their interaction.

Lowering of output impedance by DIBL

  • For short channel MOSFETs, DIBL is related to the electrical modulation of the channel length in the pinch-off region, L.

  • Since the drain current is inversely proportional to the electrical channel length, we get

for small pinch-off regions, L.

  • We assume that the fractional change in the channel length is proportional to the drain bias,

where is the channel length modulation parameter.

  • This leads to a slope in the output chanracteristics, or a lowering of the output impedance.

Short channel effect 2: Short channel effect

  • Short channel effect (SCE): VT decreases with L for very short geometries.

  • Electrical field lines are perpendicular to the equipotential contours.

  • The depletion charges that are physically underneath the agte in the approximately triangular regions near the source/drains have their field lines terminate not on the gate, but instead on the source/drains.

  • Hence, these depletion charges should not be counted in the VT expression.

  • Clearly, for a long channel device, the triangular depletion charge regions near the source and drain are very small fraction of the total depletion charge underneath the gate.

  • As the channel lengths are reduced, it results in a VTroll-off as a function of L.

  • This is important because it is hard to control the channel lengths precisely in manufacturing.

  • The channel length variation then lead to problems with VT control.

Short channel effect 3: Reverse short channel effect

  • Reverse short channel effect (RSCE).

  • Due to the interactions between Si point defects that are created during the source/drain implant and the B doping in the channel, causing the B to pile up near the source and drains, and thus raise the VT.

Short channel effect 4: Narrow width effect

  • VT goes up as the channel width Z is reduced for very narrow devices.

  • Some of the depletion charges under the LOCOS isolation regions have field lines electrically terminating on the gate.

  • The depletion charge belongs to the gate.

  • The effect becomes quite important as the widths are reduced below 1m.

6.5.12 Gate induced drain leakage

  • Gate induced drain leakage (GIDL): For even more negative gate biases we find that the off-state leakage current actually goes up as we try to turn off the MOSFET more for high VD.

Gate induced drain leakage

  • Gate induced drain leakage (GIDL): For even more negative gate biases we find that the off-state leakage current actually goes up as we try to turn off the MOSFET more for high VD.

  • As the gate is made more negative, a depletion region forms in the n-type drain.

  • Since the drain doping is high, the depletion widths tend to be narrow.

  • If the band-bending is more than the band gap Eg across a narrow depletion region, the conditions are conductive to band-to-band tunneling in this region, thereby creating electron-hole pairs.

  • The electrons then go to the drain as GIDL.

  • It must be emphasized that the tunneling is not through the gate oxide, but entirely in the Si drain region.

Moderate doping for GIDL

  • For GIDL to occur, the drain doping level should be moderate (~1018 cm-3).

    • If it is much lower that this, the depletion widths and tunneling barriers are too wide for tunneling.

    • If the doping in the drain is very high, most of the voltage drops in the gate oxide, and the band-bending in the Si drain region drops below the value Eg. No tunneling occurs..

  • GIDL is an important factor in limiting the off-state leakage current in state-of-the-art MOSFETs.