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FPGA-based Platform for Real-Time Stereo Vision

FPGA-based Platform for Real-Time Stereo Vision. Sergiy Zhelnakov, Pil Woo (Peter) Chun, Valeri Kirischian Supervisor: Dr. Lev Kirischian Reconfigurable Embedded Systems Lab Ryerson University, Toronto, ON. Motivation. Areas of application: Real-time Stereo-Vision Systems

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FPGA-based Platform for Real-Time Stereo Vision

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  1. FPGA-based Platform for Real-Time Stereo Vision Sergiy Zhelnakov, Pil Woo (Peter) Chun, Valeri Kirischian Supervisor: Dr. Lev Kirischian Reconfigurable Embedded Systems Lab Ryerson University, Toronto, ON

  2. Motivation • Areas of application: • Real-time Stereo-Vision Systems • Telematic Systems: Remote Control of Manipulators in Hazardous Areas • Virtual Reality Systems and Simulators • UAV Navigation Systems • Telemedicine • Surveillance / Security Systems

  3. Objectives • Development of the Run-Time Reconfigurable Platform for implementation, testing and real-time verification of algorithms for stereo-vision stereo-image recognition, and visualization of 3D images • Implementation and test of real-time stereo-video processing algorithms (e.g. Edge Detection in moving objects)

  4. Specification • Functional specification: • The system performs: image capture from two color cameras, stereo video visualization with shutter glasses, image processing (edge detection) • Technical specification • Input: video data with • spatial resolution 640 x 480 pixels • frame rate: 30 fps • color, 8-bit resolution • Output: standard SVGA • resolution: 640 x 480 pixels • frame rate: not less than 60 fps Fastest process: 40nS per pixel output

  5. Platform Components and Links Run-time Reconfigurable Multi-Stream Video Processor Stereo-Image Capturing & Video Pre-processing Module Video Processing Module Multi-Channel Post-processing Video-output Module Shutter Glasses LCD Projector CRT Monitor

  6. Implemented Algorithms • Color matching: (Bayer pattern) – at 2x30 frames/sec and 640x480 resolution

  7. Implemented Algorithms • Color matching

  8. 512 pixels Max (|d-a|, |b-c|) ,where a b 480 pixels c d Implemented Algorithms • Edge detection (Robert Cross) background

  9. 512 pixels Block RAM 2/1 (previous row data) a1 b1 c1 d1 e1 f1 ……………………… x1 y1 z1 512 pixels Block RAM 1/2 (current row data) A2 B2 C2 D2 E2 F2 …………………………… X2 Y2 Z2 ……… Temporary Storage P C camera DATA Calculation = C-b1 or P-a1 P : Previous camera data C : Current camera data Implemented Algorithms • Edge detection (Robert Cross)

  10. Platform Assembly and Implementation Results • Implementation results • Image capture and visualization on the FPGA based Reconfigurable Functional Unit (RFU) (1st stage - XCV50E; 2nd - XC2V1000) • Edge detection algorithm (Robert Cross) implemented

  11. Summary • The Run-Time Reconfigurable Platform was developed for different Stereo-Vision applications. • All components of the Platform were tested by implementation of real-time stereo-image capture, image processing and visualization on stereo-video output display system • Perspectives of the platform development: stereo-panoramic vision system

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