EECS150 - Digital Design Lecture 14 - Sequential Circuits I (State Elements) - PowerPoint PPT Presentation

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EECS150 - Digital Design Lecture 14 - Sequential Circuits I (State Elements)

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  1. EECS150 - Digital DesignLecture 14 - Sequential Circuits I(State Elements) March 12, 2002 John Wawrzynek EECS150 - Lec14-seq1

  2. Circuit with feedback. Examples: FSM D-type latch How about CL logic with feedback but without register? Sequential circuits exhibit either synchronous or asynchronous behavior: Synchronous: “state” of the circuit changes at regular intervals controlled by a clock. Asynchronous: state changes with changing inputs. No clock present or circuit doesn’t wait for it. Sequential Circuits EECS150 - Lec14-seq1

  3. If both R=0 & S=0, then cross-couped NORs equivalent to a stable latch: What happens if R or S or both become = 1? Cross-coupled NOR gates remember, EECS150 - Lec14-seq1

  4. Asynchronous State Transition Diagram SR Latch: EECS150 - Lec14-seq1

  5. Nand-gate based SR latch EECS150 - Lec14-seq1

  6. Level-sensitive SR Latch • The input “C” works as an “enable” signal, latch only changes output when C is high. • usually connected to clock. • Generally, it is not a good idea to use a clock as a logic signal (into gates etc.). This is a special case. EECS150 - Lec14-seq1

  7. D-latch Compare to transistor version: EECS150 - Lec14-seq1

  8. Flip-flops EECS150 - Lec14-seq1

  9. J-K FF • Add logic to eliminate “indeterminate” action of RS FF. • New action is “toggle” • J = “jam” • K = “kill” EECS150 - Lec14-seq1

  10. J-K Flip-flop from D-FF EECS150 - Lec14-seq1

  11. Toggle Flip-flop from D-FF EECS150 - Lec14-seq1

  12. Storage Element Taxonomy synchronous asynchronous level-sensitive edge-triggered D-type  n.a. JK-type n.a.  n.a. RS-type   “latch” “flip-flop” “latch” EECS150 - Lec14-seq1

  13. Design Example with RS FF • With D-type FF state elements, new state iscomputed based on inputs & present state bits - reloaded each cycle. • With RS (or JK) FF state elements, inputs are used to determine conditions under which to set or reset state bits. • Example: bit-serial adder (LSB first) With D-FF for carry EECS150 - Lec14-seq1

  14. a b ci ci+1 s Bit-serial adder with RS FF • RS FF stores the carry: Carry kill a’b’ Carry generate ab EECS150 - Lec14-seq1

  15. Resets/presets EECS150 - Lec14-seq1

  16. Adding Reset/Presets • D-type flip-flop from latches: • Asynchronous reset in Flip-flop: Either inverter (or both) can be replaced by either NOR gate or NAND gate in the second latch of the flip-flop. The second input to the gate is connected to reset or preset signal. The choice of NOR versus NAND defines the sense of the reset/preset (active-high versus active-low). The choice which inverter to replace defines reset versus preset. • Synchronous reset: A similar procedure as above is applied to the first latch of the flip-flop. Additional logic is needed to synchronize the reset signal with the correct level of the clock. D-latch circuit EECS150 - Lec14-seq1