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Lecture 5: Sequential Circuits. Soon Tee Teoh CS 147. Sequential Circuits. Combinational Circuit Output depends on input Sequential Circuit Output depends on input and state of the machine. Combinational Circuit. inputs. outputs. Storage Elements. next state. present state.

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sequential circuits
Sequential Circuits
  • Combinational Circuit
    • Output depends on input
  • Sequential Circuit
    • Output depends on input and state of the machine

Combinational

Circuit

inputs

outputs

Storage

Elements

next state

present state

From Figure 6-1, page 242

latches
Latches
  • Latch: Can maintain binary state indefinitely until directed by input signal to switch state
  • SR Latch
  • S R Q Q
  • 0 1 0
  • 0 0 1 0
  • 0 1 0 1
  • 0 0 0 1
  • 1 1 0 0

R(Reset)

Q

Set state

Reset state

Undefined

Q

S(Set)

From Figure 6-4, page 245

making sense of the sr latch
Making sense of the SR Latch
  • First, suppose that S is 1 and R is 0.
        • What are Q and Q’?
  • Then, suppose that both S and R go to 0.
        • What are Q and Q’?
  • Suppose that S is 0 and R is 1.
        • What are Q and Q’?
  • Then, suppose that both S and R go to 0.
        • What are Q and Q’?
  • Notice anything interesting?
    • S=0, R=0 give different outputs depending on previous state!
  • Suppose that S=1 and R=1.
        • What are Q and Q’?
sr latch with control input
SR Latch with Control Input
  • If C is 0, then Q cannot change, regardless of S, R.
  • If C is 1, then latch functions like SR latch.
  • C S R Next State of Q
  • 0 X X No change
  • 0 0 No change
  • 1 0 1 0
  • 1 1 0 1
  • 1 1 1 Undefined

S

Q

C

Q

R

X means whether 0 or 1

From Figure 6-7(b), page 247

d latch
D Latch
  • Undefined state in SR latch is undesirable.
  • D Latch:

D

Q

C

Q’

C D Next State of Q

0 0

0 1

1 0 0

1 1 1

No change

From Figure 6-8, page 248

symbols
Symbols

S

C

R

S

R

D

C

SR Latch

SR Latch

with

Control Input

D Latch

From Figure 6-14, page 254

flip flops
Flip-Flops
  • Problem with clock-controlled latches:
  • As long as clock is 1, change in inputs can affect outputs.
  • Consider 2 latches:

Next state/current state of Latch 1

S

C

R

S

C

R

1

2

clock

sr master slave flip flop
SR Master-Slave Flip-Flop
  • Read input at first half of clock cycle
  • Output only changed at second half of clock cycle

Slave

Master

Y

S

C

R

Q

S

C

R

S

C

R

Y

Q

From Figure 6-10, page 250

sr master slave flip flop11
SR Master-Slave Flip-Flop
  • An RS Master-Slave Flip-Flop is pulse-triggered.
  • This means:
    • Data are entered on the rising edge of the clock pulse
    • But, output is only changed on the falling edge of the clock pulse
  • Note: Changes while the clock pulse is HIGH can affect the eventual output.
    • Hence, to avoid ambiguity, make sure that the inputs are stable during the entire period while the clock pulse is HIGH.
symbol
Symbol

S

C

R

SR

Master-Slave

Flip-Flop