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RISC processor implementation using Bluespec part 1 - final presentation

17/10/2013. Performed By: Yahel Ben- Avraham and Yaron Rimmer Instructor: Mony Orbach Bi- semesterial , 2012 - 2013. RISC processor implementation using Bluespec part 1 - final presentation. Project goals. Goal: Implementing and analyzing RISC Processor using Bluespec Part A:

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RISC processor implementation using Bluespec part 1 - final presentation

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  1. 17/10/2013 Performed By: Yahel Ben-Avraham and YaronRimmer Instructor: MonyOrbach Bi-semesterial,2012 - 2013 RISC processor implementation using Bluespecpart 1 - final presentation

  2. Project goals • Goal: Implementing and analyzing RISC Processor using Bluespec • Part A: • Studying the working environment, BSV language and the basic processor implementation. • Implementing a simple RISC processor. • Run a simple test bench on the FPGA system.

  3. Pipeline Datapath • 5-stage pipeline • Pipe stages: Fetch, Decode, Execute, Memory, WriteBack • Each stage implemented as a “black box” within a separate rule. • For now, not including Data forwarding, Hazard detection. ?

  4. The Pipeline Passing structs through FIFOs FETCH2DEC MEM2WB EXE2MEM DEC2EXE Memory FETCH EXE DEC MEM WB Instruction memory Register file

  5. BSV Implementation Wrapper.bsv Defines.bsv Datapath.bsv Fetch.bsv Decode.bsv Execute.bsv Memory.bsv Writeback.bsv

  6. Fetch • Tag the instruction’s metadata (PC, cycle) • Fetch the requested instruction from the instruction memory • Update next PC

  7. Decode • Fully parse the received instruction • Pre-fetch data from registers potentially in use

  8. Execute • According to the instruction’s opcode: • ALU instruction: compute the result • Memory instruction: calculate memory address to read / write to • Branch instruction: check if branch is taken and update branch resolution and target address

  9. Memory • According to the instruction’s opcode: • Store • Load • Otherwise, pass the incoming data • Currently implemented as Register file, to be replaced by BRAM

  10. Writeback • Save needed data to the register file • Register 0 – read only

  11. The Pipeline FETCH2DEC MEM2WB EXE2MEM DEC2EXE Memory FETCH EXE DEC MEM WB Instruction memory Register file

  12. Jumps and Branches • The first 6 bits of the instruction are checked in the Fetch stage. • If Jump – next PC is immediately updated with the rest of the instruction bits. • If Branch – insert 3 NOPs to the pipeline and wait for branch resolution from the Execute stage. • Implemented easily with Bluespec!

  13. Functionality tests • Memory • Jump • Branch (taken) • Branch (not taken) • (ALU functions)

  14. Examples: Memory

  15. Examples: Jump

  16. Examples – Branch (taken)

  17. Examples: Branch (not taken)

  18. The working environment • Using a platform by ShaiShachrur and Danni Hofshi. • Allowing us to focus on the processor. • The platform enables: • Synthesis of design to FPGA. • Cycle level control using COP. • Reading and writing to memories. • Performance counters.

  19. The platform

  20. System layers

  21. Project progress overview • Studying the working environment, BSV language and the basic processor implementation. • Implementing the presented pipelined MIPS processor. • Run a simple test bench on the FPGA system. • Started planning part 2 implementations. • Up next…

  22. Up Next

  23. Questions?

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