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Final presentation- Part BPowerPoint Presentation

Final presentation- Part B

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- Linux on SOPC – LFSR Decryption on Linux Based System

Final presentation- Part B

Avi Urman, Kobi Maltinsky

Supervisor: Inna Rivkin

- Project Goals
- Algorithm Overview
- Software Based Decryption/Encryption
- Hardware Based Decryption/Encryption
- FSL
- Boot Up
- TFT Screen
- Difficulties
- Part B

- Part A - Implement an interactive standalone embedded system running Linux.

- Interaction with user through PS/2 keyboard
- LCD Screen as standard output of the system
- Ethernet
- UART
- Boot system from flash
- AC97 Codec For Audio Support

Linux

- Part B - Based on system from part A, create a Hardware Accelerator – Decode an encrypted file using software and hardware.

- Write a software encoder that will run on host CPU , encode a sound file.
- Write a software based decoder that will run on our system, read file through Ethernet I/F.
- show that it’s not fast enough to perform decoding in real time.
- Write a hardware decoder in VHDL and integrate into existing system.
- Show that decoding works well with the hardware offload engine, and the sound file plays ok.

Encryption/Decryption Algorithm

- Encryption/Decryption was based on LFSR – Linear Feed Back Register.
- LFSR is most often a shift register whose input bit is driven by the exclusive-or (XOR) of some bits of the overall shift register value.
- Because operation of the register is deterministic, the stream of values produced by the register is completely determined by its current (or previous) state.

Encryption/Decryption Algorithm - Continued

- First an initial parameters are chosen : Initial seed, number of bits to be XORed on each round ,number of cycles to shift on each round and the feedback polynomial taps.
- During encryption , bits from the file are XOR’ed with the LFSR value after several hundred shifts and written back to the encrypted file.
- Value of the LFSR register is saved and same process repeated for the next bits
- For decoding, we need to know the same parameters(seed,cycles,taps). Decoding process is the same, XORing the encrypted bits with the LFSR value preserves the original value

Software Based Decoding Overview

- Host and Microblaze run pretty similar programs.
- Host reads 32 bit from file performs algorithm and writes to Ethernet through standard Linux API .
- Microblaze reads 32 bit from Ethernet I/F performs same algorithms and writes the data to FSL link.
- Data goes from FSL link to AC97 codec through ac97 controller, data is not changed through hardware

Host Encryption

for (count = fread(&buf, 1, 4, inFile); count != 0; count = fread(&buf, 1, 4, inFile))

{

for (i = 0; i < cycles; ++i) {

/* taps: 16 14 13 11; characteristic polynomial: x^16 + x^14 + x^13 + x^11 + 1 */

bit = ((lfsr >> 15) ^ (lfsr >> 13) ^ (lfsr >> 12) ^ (lfsr >> 10)) & 1;

lfsr = (lfsr >> 1) | (bit << 31);

}

buf ^= lfsr;

printf("%u\n",lfsr);

fwrite(&buf, 1, count, outFile);

MicroBlazeDecryptor- Ethernet I/F

/* Connection initialization: */

/* get an internet domain socket */

if ((sd = socket(AF_INET, SOCK_STREAM, 0)) == -1) {

perror("socket");

exit(1);

}

/* complete the socket structure */

memset(&sin, 0, sizeof(sin));

sin.sin_family = AF_INET;

sin.sin_addr.s_addr = INADDR_ANY;

sin.sin_port = htons(PORT);

/* Avoid the "bind: Address already in use" problem */

setsockopt(sd, SOL_SOCKET, SO_REUSEADDR, (const char *) &iSocketOption, sizeof(int));

/* bind the socket to the port number */

if (bind(sd, (structsockaddr *) &sin, sizeof(sin)) == -1) {

perror("bind");

close(sd);

exit(1);

}

/* show that we are willing to listen */

if (listen(sd, 5) == -1) {

perror("listen");

close(sd);

exit(1);

}

/* wait for a client to talk to us */

addrlen = sizeof(pin);

if ((sd_current = accept(sd, (structsockaddr *) &pin, &addrlen)) == -1) {

perror("accept");

close(sd);

exit(1);

}

MicroBlazeDecryptor- Decryption Process

/* We decrypt data before playing it at this point */

if(first_iter_flag==1)

{

lfsr_State=doDecryption((uint32_t *)buffer,1010110);

first_iter_flag=0;

}

else

lfsr_State=doDecryption((uint32_t *)buffer,lfsr_State);

while(currentWriteOffset < currentReadOffset) {

unsigned intwriteLen = write(fsl_fd,

&(buffer[currentWriteOffset]),

currentReadOffset-currentWriteOffset);

if(writeLen <= 0) {

perror("write");

close(sd_current);

close(sd);

exit(1);

}

currentWriteOffset += writeLen;

}

if(currentReadOffset < N) {

printf("Transfer done, exiting\n");

close(sd_current);

close(sd);

break;

/* Main data pumping loop: */

while(1) {

size_tcurrentReadOffset = 0;

size_tcurrentWriteOffset = 0;

while(currentReadOffset < N)

{

/* get some more data from the client */

unsigned intreadLen = recv(sd_current,

&(buffer[currentReadOffset]),

N-currentReadOffset, 0);

if(readLen == -1)

{

perror("recv");

close(sd_current);

close(sd);

exit(1);

}

currentReadOffset += readLen;

if(readLen == 0)

{

break;

}

MicroBlazeDecryptor- LFSR Block

uint32_t doDecryption(uint32_t *buf,uint32_t lfsr)

{

uint32_t bit;

inti,j;

intnum_of_elements=N/sizeof(uint32_t);

for (i = 0; i <num_of_elements ; i++)

{

for (j = 0; j < NUM_OF_SHIFTS; ++j)

{

/* taps: 16 14 13 11; characteristic polynomial: x^16 + x^14 + x^13 + x^11 + 1 */

bit = ((lfsr >> 15) ^ (lfsr >> 13) ^ (lfsr >> 12) ^ (lfsr >> 10)) & 1;

lfsr = (lfsr >> 1) | (bit << 31);

}

buf[i]^=lfsr;

}

return lfsr;

}

FSL Link

- Fast Simplex Link is a 32-bits wide interface on MicroBlaze.
- The FSL channels are uni-directional, point-to-point data streaming interfaces.
- The FSL can be used for extending the processor execution unit with custom hardware accelerators thanks to a low latency dedicated interface to the processor pipeline.
- In addition, the same fsl channel can be used for the transmit or receive either control or data words. A separate bit indicates whether the transmitted (receive) word is control or data information..

Block I/F

entity ac97_fsl_link is

port

(

AC97Reset_n : out std_logic; -- AC97Clk

AC97Clk : in std_logic;

Sync : out std_logic;

SData_Out : out std_logic;

SData_In : in std_logic;

--for debug

LFSR_cnt_output : out std_logic_vector (8 downto 0);

LFSR_Register_output : out std_logic_vector (31 downto 0);

Shifitng_Done_output : out std_logic;

current_state_output : out std_logic_vector (1 downto 0);

FSL_S_Data_output : out std_logic_vector(0 to 31);

Shifted_Data_output : out std_logic_vector(0 to 31);

FSL_S_Read_output : out std_logic;

FSL_S_Exists_output : out std_logic;

-- DO NOT EDIT BELOW THIS LINE ---------------------

-- Bus protocol ports, do not add or delete.

FSL_Clk : in std_logic;

FSL_Rst : in std_logic;

FSL_S_Clk : out std_logic;

)

FSM

AC_97_FSL_logic : process (current_state, playback_accept, FSL_S_Exists, record_valid, FSL_S_Data,Shifitng_Done,LFSR_Register) is

begin -- process AC_97_FSL_logic

case current_state is

when Idle =>

if (FSL_S_Exists = '1' AND playback_accept = '1') then

next_state <= Perform_Shifting ;

else

next_state <= Idle;

end if;

when Perform_Shifting =>

if (Shifitng_Done='1') then

next_state <= Read_Inputs ;

else

next_state <= Perform_Shifting ;

end if;

when Read_Inputs =>

playback_left <= FSL_S_Data(0 to 15) xorLFSR_Register(31 downto 16);

playback_right <= FSL_S_Data(16 to 31) xorLFSR_Register(15 downto 0);

next_state <= Idle;

end case;

end process AC_97_FSL_logic;

LFSR Block

LFSR_Reg : process (FSL_Clk) is

variable Feed_Back1 :std_logic;

variable Feed_Back2 :std_logic;

variable Feed_Back3 :std_logic;

variable Feed_Back4 :std_logic;

variable Tmp_LFSR_Register :std_logic_vector (31 downto 0);

begin -- process LFSR_Reg

if FSL_Clk'event and FSL_Clk = '1' then -- Rising clock edge

if FSL_Rst = '1' then -- Synchronous reset (active high)

LFSR_Register<= Initial_LFSR_Value;

else

if current_state = Perform_Shifting then

Feed_Back1 := LFSR_Register(15) xorLFSR_Register(12) xorLFSR_Register(13) xorLFSR_Register(10) ;

Tmp_LFSR_Register:= Feed_Back1 & LFSR_Register(31 downto 1) ;

Feed_Back2 := Tmp_LFSR_Register(15) xorTmp_LFSR_Register(12) xorTmp_LFSR_Register(13) xorTmp_LFSR_Register(10) ;

Tmp_LFSR_Register:= Feed_Back2 & Tmp_LFSR_Register(31 downto 1) ;

Feed_Back3 := Tmp_LFSR_Register(15) xorTmp_LFSR_Register(12) xorTmp_LFSR_Register(13) xorTmp_LFSR_Register(10) ;

Tmp_LFSR_Register:= Feed_Back3 & Tmp_LFSR_Register(31 downto 1) ;

Feed_Back4 := Tmp_LFSR_Register(15) xorTmp_LFSR_Register(12) xorTmp_LFSR_Register(13) xorTmp_LFSR_Register(10) ;

LFSR_Register<= Feed_Back4 & Tmp_LFSR_Register(31 downto 1) ;

end if;

end if;

end if;

end process LFSR_Reg;

Debug Wave From Chipscope

Performance

- Number of shifts of LFSR per 32 bit was the main bottleneck for performance .
- Through few experiments we’ve found that Software decoding works good on low count shifts <150 .
- For a large amount of shifts , software decoding breaks , results in improper play of the sound file.
- Hardware decoding worked well for extremely large amount of shifts.

Booting Up-Reminder

- A single “ACE” file was created containing Hardware and Software.
- The file was place in Compact Flash, and read by FPGA through JTAG on power up.
- After Hardware design is downloaded, FPGA copies kernel to the DDR memory through MDM interface
- while loading the kernel file to memory, we had to prevent the processor executing random code and keep it in a known state, thus a simple C program was created ,which waits a few seconds (until the compact flash finished copying the kernel) and the jumps to 0x50000000 where the kernel resides in memory.

Difficulties

- Debugging was difficult and consumed the majority of the time.
- Lots Of component's HW + SW.
- Timing Problems.
- Endianess Problem.

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