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Implementing and Analyzing a RISC Processor Using Bluespec: Winter 2012 Project

This project, conducted by Yahel Ben-Avraham and Yaron Rimmer under the guidance of Mony Orbach in Winter 2012, focuses on implementing and analyzing a RISC processor using Bluespec SystemVerilog (BSV). The goals include setting up a working environment, synthesizing the RISC design onto FPGA, and conducting performance analyses. Participants engage in simulations, modify design files, and use SignalTap for real-time performance evaluation. The project aims to enhance understanding of microprocessor architecture and develop practical skills in digital design.

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Implementing and Analyzing a RISC Processor Using Bluespec: Winter 2012 Project

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  1. 3/12/2012 Performed By: Yahel Ben-Avraham and YaronRimmer Instructor: MonyOrbach Semesterial (possibly bi-semesterial) Winter 2012 Implementing and Analyzing RISC Processor using Bluespeccharacterization presentation

  2. Introduction • BSV (Bluespec SystemVerilog) • High level language • Fully synthesizable • High simulation capabilities • RISC processor • (Reduced Instruction Set Computer) • Simple capabilities: pipeline, cache, branch prediction…

  3. Project goals • Goal: Implementing and analyzing RISC Processor using Bluespec • Sub-goals: • Learning the working environment and Implementing simple BSV designs • Setup and simulate a (modified) RISC processor in BSV environment • Synthesize the processor onto FPGA and run tests using SignalTap • Performance analysis

  4. Work flow

  5. Working environment

  6. Studying the environment • Setting up the environment • Learning the working environment and Implementing simple BSV designs • 046004 - Architecting and Implementing Microprocessors in Bluespec(summer 2012 course) Lectures and lab exercises. • BSV by example (pdf)

  7. Setting up the RISC processor(virtually) • Studying the RISC processor’s general design • Modifying the processor design files

  8. Running simulations and familiarizing with the processor • In-Depth studying of the RISC processor design • Running simulations • Running testbenches • See the processor in action

  9. Synthesis and analyzing(SignalTap) • Synthesizing the virtual design and downloading to board • Will be using ML605 or ML505 • Running testbenches on the downloaded design • Using SignalTap to analyze the performance of the processor

  10. Performance analysis • Assess the processor’s capabilities: • Instructions Per Cycle • Throughput • Latency And perhaps more • Target capabilities will be decided in mid-project presentation.

  11. Timeline

  12. General Timeline - project

  13. Questions?

  14. Or else… When in doubtmake it simple !

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