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Ch.6 Logic Verification

Standard Cell Design. Ch.6 Logic Verification. TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology. How to confirm the correctness of design result 50-70% of design period is used for design verification. Methods Logic Simulation and Emulation

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Ch.6 Logic Verification

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  1. Standard Cell Design Ch.6 Logic Verification TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology

  2. How to confirm the correctness of design result 50-70% of design period is used for design verification. Methods Logic Simulation and Emulation Formal Verification Design Verification

  3. Logic Design RTL RTL Simulation Logic Synthesis Synthesis Netlist Functional Verification Scan Path Design Functional Verification Scan Netlist Timing Analysis

  4. 6.1 Logic Simulation

  5. Logic Design 1HDL Simulation [Objective] to correct HDL description by simulating its performance and checking its timing due to delays of logic circuit. [Method] 1. HDL/Logic Simulator

  6. Logic Design 1Four Valued Logic Not only 0 and 1, but other values such as UNKNOWN X, HIGH IMPEDANCE Z are used for the simulation. Their response are described by truth table. Truth Table of AND Gate

  7. Simulation Method 1. Event Driven Simulation Outputs of the gates has been evaluated by truth table , only when an event occurs on inputs of the gates. Since small portion of whole circuit works at a time, this scheme avoid waste computation. Thus, simulator keeps track of those events. 2. Time wheel Event Table Change of outputs of the gates are stored as an event. That event occurs delayed at component delay after event of inputs occurs. The time of next events are stored in event table. The table is considered to be wheel so that it can store events of all simulation periods, efficiently.

  8. Event Driven • Event is a change of logic value. • The event entered into a gate may • generate another event at the output • of the gate after the gate delay time. • Event of Signals propagates through • Logic circuits. • Event Driven Analysis is to update • Logic values only when events occur • at the wire so as to minimize • computational complexity. • 30% or less logic parts is running at • the same time.

  9. Logic Simulation Example

  10. 6.2 Formal Verification

  11. Formal Verification RTL RTL Simulation Logic Synthesis Scan Netlist Functional Verification Scan Path Design Functional Verification Synthesis Netlist Timing Analysis

  12. Logic Design 3Formal Verification [Objective] to confirm coincidence between HDL description and designed logic circuit. Simulation uses various test inputs, while formal verification uses equivalence of two functions. [Method] BDD method (Binary Decision Diagram) It is effective way to show equivalent representation of logic functions for two targets. [Problem] 1. Reduction of scan path flip flops 2. Speed up of testing such as concurrent testing

  13. 0 1 1 0 0 1 1 1 0 1 0 0 0 1 Logic Design 3BDD Representation 1 BDD representation will be unique according to the best variable order. There was heuristic algorithm to derive the reduced BDD from original.

  14. BDD Operation (1) Merge of 2 isomorphic subgraphs

  15. BDD Operation (1) Merge of 2 isomorphic subgraphs

  16. BDD Operation (2) Eliminate node, whose son nodes are isomorphic.

  17. BDD Operation (2)

  18. X3 X3 X3 X5 X5 X5 X5 X2 X2 X2 X2 X2 X4 X4 X1 X1 X6 X4 X6 X5 Order of nodes X1 X2 X3 X4 X5 X6 Ｗｏｒｓｔ Ｂｅｓｔ 0 0 1 1

  19. i i-1 i i-1 i i-1 i-1 i i i-1 i i+1 i+1 i+1 i+1 i+1 i+1 i+1 i+1 Optimal Order Search 0 1 0 1 (B) (C) (C) (B) (A) (D) (A) (D) 1 0 0 1 f1 f2 f3 f1 f2 f3

  20. Verification exampleI d1=q1q0’+a’q1+ｂq0 ｄ0=bq1’q0’+a’bq1’+a’ｂq0’

  21. Verification exampleII F1=q0’・a’ a’ (F1+F2)’ q0’ q0’+a’ q1’ F2=(q0’+a’)q1‘ F1=q0’・a’の 補正のため 葉の0 と１を 交換

  22. Verification exampleIII ｄ0=bq1’q0’+a’bq1’+a’ｂq0’

  23. 6.3 Timing Analysis

  24. Timing Analysis Timing Analysis is to check the timing violation of logic circuits, due to gate delays and wire delays. In order to reduce computation, critical paths analysis is done by using graph representation. Pre Layout timing analysis: Only gate delay is considered. Post Layout timing analysis: Gate delay and wire delay are considered. The latter delays are decided by layout pattern. This analysis is only performed after layout design.

  25. Timing Analysis • ․Calculate timing of synthesized netlist ⎯ Make sure circuit operates correctly under specified timingconstraints • ․Static Timing Analysis (STA) ⎯ Timing analysis without input patterns 　　－Fast but not accurate ⎯ Used after logic synthesis • ․Dynamic Timing Analysis ⎯ Timing analysis with input patterns ⎯ Slow but accurate ⎯ Used after physical design with few patterns

  26. Logic Design 5Timing Analysis (Pre) • Timing Analysis identifies critical path with graph model, instead of exhausted search with logic simulator.

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