MAPS ECAL

1. MAPS ECAL SiD Workshop RAL 14-16 Apr 2008 • Technical Status • Future Plans • Summary Nigel Watson Birmingham University For the CALICE MAPS group J.P.Crooks, M.M.Stanitzki, K.D.Stefanov, R.Turchetta, M.Tyndel, E.G.Villani (STFC-RAL) J.A.Ballin, P.D.Dauncey, A.-M.Magnan, M.Noy (Imperial) Y.Mikami, O.D.Miller, V.Rajovic, NKW, J.A.Wilson (Birmingham)

2. MAPS ECAL: basic concept • Swap ~0.5x0.5 cm2 Si pads with small pixels • “Small” := at most one particle/pixel • 1-bit ADC/pixel, i.e. Digital ECAL Effect of pixel size • How small? • EM shower core density at 500GeV is ~100/mm2 • Pixels must be<100100mm2 • Our baseline is 5050mm2 • Gives ~1012 pixels for ECAL – “Tera-pixel APS” 50mm Weighted no. pixels/event >1 particle/ pixel 100mm Incoming photon energy (GeV) SiD Workshop, RAL, 15-Apr-2008

3. New since Jan. workshop? • What is it sensible to show? • Results from testbeam?? • Hints that we are starting to understand what is going on? • JB evt display? Layer-layer correlation plots a la TM? • Etc? SiD Workshop, RAL, 15-Apr-2008

4. CALICE INMAPS TPAC1 0.18mm feature size First round, four architectures/chip (common comparator+readout logic) INMAPS process: deep p-well implant 1 μm thick under electronics n-well, improves charge collection Architecture-specific analogue circuitry 4 diodes Ø 1.8 mm SiD Workshop, RAL, 15-Apr-2008

5. The CALICE TPAC1 • 50x50 mm cell size • Comparator per pixel • Capability to mask individual pixels • 4 Diodes for ~uniform response w.r.t threshold • 13 bit time stamp (>8k bunches individually tagged) • Hit buffering for entire bunch train (~ILC occupancy) • Threshold adjustment for each pixel • Usage of INMAPS (deep-p well) process [Marcel Stanitzki] SiD Workshop, RAL, 15-Apr-2008

6. TPAC1 overview • 8.2 million transistors • 28224 pixels; 50 microns; 4 variants • Sensitive area 79.4mm2 • Four columns of logic + SRAM • Logic columns serve 42 pixels • Record hit locations & timestamps • Local SRAM • 11% deadspace due to readout/logic • Data readout • Slow (<5 MHz) • Current sense amplifiers • Column multiplex • 30 bit parallel data output “region” “Group” (region=7 groups of 6 pixels) SiD Workshop, RAL, 15-Apr-2008

7. Attention to detail 2: beam background purple = innermost endcap radius 500 ns reset time  ~ 2‰ inactive pixels • Beam-beam interaction by GUINEAPIG • LDC01sc (Mokka) • 2 machine scenarios studied : • 500 GeV baseline, • 1 TeV high luminosity y (mm) Study to be repeated in SiD01 Verify optimisation [O.Miller] X (mm) SiD Workshop, RAL, 15-Apr-2008

8. Progress with sensor tests Work ongoing to test unformity of threshold and gain Report today on testbeam SiD Workshop, RAL, 15-Apr-2008

9. Hit buffering for train SiD Workshop, RAL, 15-Apr-2008

10. MAPS testbeam • Desy 10-17 Dec. 2007 • Extremely tight schedule… • 4 sensors, PMT coincidence trigger • 3, 6 GeV e- • With/without tungsten pre-shower material • Threshold scans • USB_DAQ SiD Workshop, RAL, 15-Apr-2008

11. SiD Workshop, RAL, 15-Apr-2008

12. SiD Workshop, RAL, 15-Apr-2008

13. PMT trigger SiD Workshop, RAL, 15-Apr-2008

14. Sensor setup in testbeam SiD Workshop, RAL, 15-Apr-2008

15. SiD Workshop, RAL, 15-Apr-2008

16. Concentrate on shapers SiD Workshop, RAL, 15-Apr-2008

17. Strategy • Want to start with the highest purity sample we can • Scintillators behaviour “not optimal” • Ensure sensor hits genuine • Use clusters of hits initially, not single pixels • Can we match clusters between sensors? SiD Workshop, RAL, 15-Apr-2008

18. Clustering SiD Workshop, RAL, 15-Apr-2008

19. Layer-layer correlations: x SiD Workshop, RAL, 15-Apr-2008

20. Layer-layer correlations: y SiD Workshop, RAL, 15-Apr-2008

21. Layer-layer alignment SiD Workshop, RAL, 15-Apr-2008

22. …and funding • Recognised as generic technology • Much interest to continue development of concept for ECAL • Including for SiD • … SiD Workshop, RAL, 15-Apr-2008

23. MAPS summary • Concept of CMOS MAPS digital ECAL for ILC • Multi-vendors, cost/performance gains • New INMAPS deep p-well process (optimise charge collection) • Four architectures for sensor on first chips, delivered to RAL Jul 2007 • Tests of sensor performance in progress: sources, charge diffusion, cosmics, testbeam • Physics benchmark studies, compare MAPS vs. analogue Si-W designs • In framework of SiD and IDC detector concepts SiD Workshop, RAL, 15-Apr-2008

24. Summary • MAPS ECAL: alternative to baseline design (analogue SiW) • Multi-vendors, cost/performance gains • New INMAPS deep p-well process (optimise charge collection) • Four architectures for sensor on first chips • Tests of sensor performance ongoing • Physics benchmark studies with MAPS ECAL to evaluate performance relative to standard analogue Si-W designs, for both SiD (and ILD) detector concepts • Future plans • Systematic studies of pixel to pixel gain and threshold variations • Absolute gain calibration • Second sensor… SiD Workshop, RAL, 15-Apr-2008

25. Backup slides… SiD Workshop, RAL, 15-Apr-2008

26. Type dependant area: capacitors, and big resistor or monostable Architectures on ASIC1 Presampler Preshaper SiD Workshop, RAL, 15-Apr-2008