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Excitation Vectors

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Input. Combinational Logic. Output. Excitation Vectors. States. Memory. RS Latch Q+ = S + R’ Q. Two Problems: R=S= 1 Not allowed, Data is transparent. The D Latch. Problem: Level sensitive. JK Latch : Universal, Level sensitive, Timing Constraints due to feed back. .

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Presentation Transcript
slide1

Input

Combinational Logic

Output

Excitation Vectors

States

Memory

slide2

RS Latch

Q+ = S + R’ Q

Two Problems:

R=S= 1 Not allowed, Data is transparent

slide3

The D Latch

Problem: Level sensitive

slide4

JK Latch : Universal, Level sensitive,

Timing Constraints due to feed back.

slide5

Master Slave Flip Flop

Edge sensitive,Set up and Hold time

slide6

Master Slave Flip Flop Edge sensitive,-Falling Edge

Set Up and Hold Time constraints

Path to setup data

Master

Slave

Q

Q

Q

D

D

D

D

D

Latch

Latch

Q

C

C

C

Path to hold data

D

C

Q

slide7

Edge triggered Flip Flop:

Set up and Hold time Constraints

slide8

Edge Triggered, D Flip Flop

NAND1

S

Q

NAND2

NAND5

clk

R

NAND3

NAND6

D

NAND4

reset

slide9

NAND1

S

Q

NAND2

NAND5

clk

R

NAND3

NAND6

D

NAND4

reset

When CLK changes from 0 to 1

Case1, D=0: tsetup= t4, thold=t3

Case2, D=1 tsetup=t4 + t1 thold= t2

slide10

NAND1

S

Q

NAND2

NAND5

clk

R

NAND3

NAND6

D

NAND4

reset

When CLK changes from 0 to 1

Case1, D=0: tsetup= t4, thold=t3

Path for hold

Path for set up

slide11

NAND1

S

Q

NAND2

NAND5

clk

R

NAND3

NAND6

D

NAND4

reset

When CLK changes from 0 to 1

Case2, D=1 tsetup=t4 + t1 thold= t2

Path to set up

Path to hold

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