8086 & Z80 µP. Lec note 2. Outline. Microprocessors History Data width 8086 vs 8088 8086 pin description Z80 Pin description. Microprocessors. Microprocessors come in all kinds of varieties from the very simple to the very complex
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Lec note 2
Only external bus of 8088 is 8_bit
8_bit Data Bus
16_bit Data Bus
Vcc (pin 40) : Power
Gnd (pin 1 and 20) : Ground
AD0..AD7 , A8..A15 , A19/S6, A18/S5, A17/S4, A16/S3 : 20 -bit Address Bus
MN/MX’ (input) : Indicates Operating mode
READY (input , Active High) : take µP to wait state
CLK (input) : Provides basic timing for the processor
RESET (input, Active High) : At least 4 clock cycles Causes the µP immediately
terminate its present activity.
TEST’ (input , Active Low) : Connect this to HIGH
HOLD (input , Active High) : Connect this to LOW (BR)
HLDA (output , Active High) : Hold Ack (BG)
INTR (input , Active High) : Interrupt request
INTA’ (output , Active Low) : Interrupt Acknowledge
NMI (input , Active High) : Non-maskable interrupt
DEN’ (output) : Data Enable. It is LOW when processor wants to
receive data or processor is giving out data (to74245)
DT/R’ (output) : Data Transmit/Receive.
WhenHigh, data from µP to memory
When Low, data is from memory to µP (to74245 dir)
IO/M’ (output) : If High µP access I/O Device.
If Low µP access memory
RD’ (output) : When Low, µP is performing a read operation
WR’ (output) : When Low, µP is performing a write operation
ALE (output) : Address Latch Enable , Active High
Provided by µP to latch address
When HIGH, µP is using AD0..AD7, A19/S6,
A18/S5, A17/S4, A16/S3 as address lines
Address bus (output, active high, 3-state).
Used for accessing the memory and I/O ports
During the refresh cycle the I is put on this bus.
Data Bus (input/output, active high, 3-state). Used for data exchanges with memory, I/O and interrupts.
Read (output, active Low, 3-state) indicates that the CPU wants to read data from memory or I/O
Write (output, active Low, 3-state) indicates that the CPU data bus holds valid data to be stored at the addressed memory or I/O location.
Memory Request (output, active Low, 3-state). Indicates memory read/write operation. See M1
Input/Output Request(output,active Low,3-state) Indicates I/O read/write operation. See M1
Machine Cycle One (output, active Low).
Together with MREQ indicatesopcode fetch cycle Together with IORQ indicates an Int Ack cycle
Refresh (output, active Low).
Together with MREQ indicates refresh cycle.
Lower 7-bits address is refresh address to DRAM
MREQ, IORQ, RD, and WR to high-imp.
address, data, and control signals
have entered their high-impedance states.
what is this instruction useful for?
S Sign Flag (1:negativ)*
Z Zero Flag (1:Zero)
H Half Carry Flag (1: Carry from Bit 3 to Bit 4)**
P Parity Flag (1: Even)
V Overflow Flag (1:Overflow)*
N Operation Flag (1:previous Operation was subtraction)**
C Carry Flag (1: Carry from Bit n-1 to Bit n,with n length of operand)
*: 2-complement number representation
**: used in DAA-operation for BCD-arithmetic
Adjusts the content of the Accumulator A for BCD addition and subtraction
operations such as ADD, ADC, SUB, SBC, and NEG according to the table:
During I/O operations a single wait state is automatically inserted
Two wait states are automatically added to this cycle
There are two types of interrupts: