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Input-Output Pads. VLSI Digital System Design. Input-Output Pad Design. I-O pad design is highly specialized Requires circuit design experience Requires fabrication process understanding Choose already-characterized library from: Fabrication vendor Third-party library vendor

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input output pad design
Input-Output Pad Design
  • I-O pad design is highly specialized
    • Requires circuit design experience
    • Requires fabrication process understanding
  • Choose already-characterized library from:
    • Fabrication vendor
    • Third-party library vendor
    • In-house group
pad size and spacing
Pad Size and Spacing
  • Pad size
    • Smallest to which a wire can be bonded
    • 100 – 150 μm
  • Pad spacing
    • Smallest to which a bonding machine can bond
    • 150 – 200 μm
interdigitated pads

I-O circuitry

Interdigitated Pads
  • Allows more pads on die
ibm c4 i o pads
IBM C4 I-O Pads
  • Bonding wires restrict I-O pads to die edge
  • IBM C4 I-O pads can also be on interior of chip
    • Deposit solder ball on I-O pad
    • Heat die and board to reflow solder
    • Solder surface tension positions die on board
latchup
Latchup
  • Latchup occurs when voltage excursion outside VSS < v < VDD
  • Most likely at I-O pad
    • Large transistors
    • High current
    • Inductance of bonding wire
    • Connection to external circuitry
output pad latchup prevention
Output Pad Latchup Prevention
  • Separate the nMOS and pMOS transistors
  • Separate the power supplies for I-O frominternal logic
  • Guard rings
guard rings
Guard Rings
  • Ohmic contacts to metal
    • p+ diffusion in p-substrate
    • n+ diffusion in n-well
  • Collect minority carriers
    • Injected into substrate whendrain diodes are forward-biased
  • Rings should be continuous diffusion
    • No crossovers
double guard rings
Double Guard Rings
  • Surround nMOS transistor by:
    • p+ connection to VSS, surrounded by
    • n-well with n+ connection to VDD
  • Surround pMOS transistor by:
    • p+ ring connected to VDD, surrounded by
    • n-well with n+ connection to VSS
use smaller transistors in parallel
Use Smaller Transistors in Parallel
  • Minimize gate
    • Reduce RC delay
    • I-O pad transistors often have long gates
      • Improve avalanche breakdown characteristics
  • Parallel metal-transistor connections
    • Minimize metal migration
input pad esd protection
Input Pad ESD Protection
  • If not VDD <= X <= VSS,one of the clamp diodes turns on
    • Use double guard rings
  • Resistor R limits current in clamp diode
    • 200 Ω <= R <= 3000 Ω
    • Tub resistor
      • For n-well process: p-diffusion
  • C is input capacitance
    • Speed of signal limited by RC
punch through device
Punch-Through Device
  • Built of closely-spacedsource and drain diffusions
    • No gate
  • “Avalanches” at c. 50 V
pull up or pull down resistor
Pull-Up or Pull-Down Resistor
  • Long pMOS transistor
  • Long nMOS transistor
  • Connect gate to signal for IDDQ testing