Simultaneous Power and Thermal Integrity Driven Via Stapling in 3D ICs

1. Simultaneous Power and Thermal Integrity Driven Via Stapling in 3D ICs My presentation topic is about a Simultaneous Power and Thermal Integrity Driven Via Stapling in 3D ICs. We are partially supported by NSF and UC-Micro fund from Intel. My presentation topic is about a Simultaneous Power and Thermal Integrity Driven Via Stapling in 3D ICs. We are partially supported by NSF and UC-Micro fund from Intel.

2. 2 New Solution for High-performance Integration 2D SoC is limited by the device density and interconnect performance such as delay. One promising solution is to use the third dimension to further pack devices and reduce interconnect delay. The enabling technology for such a 3D IC includes: Chip-level Wafer Bonding or Die-level Silicon Epitaxial Growth. For the die level 3D integration, a conceptual diagram for 3D IC is shown below. It includes heat sink on top, active device layer, inter-layer dielectric, inter-layer via and power supply planes on bottom. Such a integration also brings extra challenges. As discussed in this paper, we to need consider both thermal and power integrities in design. 2D SoC is limited by the device density and interconnect performance such as delay. One promising solution is to use the third dimension to further pack devices and reduce interconnect delay. The enabling technology for such a 3D IC includes: Chip-level Wafer Bonding or Die-level Silicon Epitaxial Growth. For the die level 3D integration, a conceptual diagram for 3D IC is shown below. It includes heat sink on top, active device layer, inter-layer dielectric, inter-layer via and power supply planes on bottom. Such a integration also brings extra challenges. As discussed in this paper, we to need consider both thermal and power integrities in design.

3. 3 Thermal Challenge in 3D ICs Because the dielectric layer are poor thermal conductors, Temperature of each die increases along third dimension as shown in this figure. Heat sink is on the top� High temperature has already been an issue for 2D chips. It could affect interconnect and device reliability and lead to variations to timing. Therefore, a 3D IC design tool has to consider the thermal problem. One solution is to staple good thermal conductors such as inter-layer vias can remove the heat.Because the dielectric layer are poor thermal conductors, Temperature of each die increases along third dimension as shown in this figure. Heat sink is on the top� High temperature has already been an issue for 2D chips. It could affect interconnect and device reliability and lead to variations to timing. Therefore, a 3D IC design tool has to consider the thermal problem. One solution is to staple good thermal conductors such as inter-layer vias can remove the heat.

4. 4 Power Delivery Challenge in 3D ICs In addition, note that The voltage bounce is significant in P/G planes at the bottom due to resonance. Large voltage bounce affects the performances of I/Os. Interestingly, because Vertical vias can minimize the returned current path and hence loop inductance They can be also used as power vias to reduce the voltage bounce for each P/G plane. In addition, note that The voltage bounce is significant in P/G planes at the bottom due to resonance. Large voltage bounce affects the performances of I/Os. Interestingly, because Vertical vias can minimize the returned current path and hence loop inductance They can be also used as power vias to reduce the voltage bounce for each P/G plane.

5. 5 Via Planning Problem in 3D IC Previous work (thermal via planning) Iterative via planning during placement [Goplen-Sapatnekar:ISPD�05] Alternating-direction via planning during routing [Zhang-Cong:ICCAD�05] Both use steady-state thermal analysis and ignore variant thermal power Both ignore that the vertical via can be also designed to remove the voltage bounce in power supply Based on the above observations, we propose to Staple vias from the top heat-sink to the bottom P/G planes. As a result, it can remove heat in silicon die and reduce voltage bounce in package plane. There are following existing works about via planning in 3D IC. Goplen proposed an iterative via planning during placement. Zhang proposed an alternating direction via planning during routing. These two methods both use a steady-state analysis and assume a maximum-thermal power. As shown by our paper, they may lead to over-design, i.e., unnecessary number of vias. In this paper, we propose to minimize a thermal violation integral with the constraint of routing congestion. The solution algorithm is based on an efficient sensitivity-driven sequential programming with the use of macromodel. Our key contribution is to apply macromodel based transient thermal analysis for via planning to avoid over design. Based on the above observations, we propose to Staple vias from the top heat-sink to the bottom P/G planes. As a result, it can remove heat in silicon die and reduce voltage bounce in package plane. There are following existing works about via planning in 3D IC. Goplen proposed an iterative via planning during placement. Zhang proposed an alternating direction via planning during routing. These two methods both use a steady-state analysis and assume a maximum-thermal power. As shown by our paper, they may lead to over-design, i.e., unnecessary number of vias. In this paper, we propose to minimize a thermal violation integral with the constraint of routing congestion. The solution algorithm is based on an efficient sensitivity-driven sequential programming with the use of macromodel. Our key contribution is to apply macromodel based transient thermal analysis for via planning to avoid over design.

6. 6 Outline Modeling and Problem Formulation Integrity Analysis and Sensitivity based Optimization Experimental Results Conclusions In the following I�ll first review the background of thermal analysis and then present out problem formulation. In the following I�ll first review the background of thermal analysis and then present out problem formulation.

7. 7 Electric and Thermal Duality Let�s first review the well-known thermal-electrical duality. The table shows that the temperature corresponds to the electrical voltage response, and the thermal power corresponds to the input current sources. In addition, there exist the corresponding thermal conductance and capacitance. Animation As a result, the thermal system could be also described by MNA based state equation in both time and frequency domain. In addition, as shown later on, because the via conductance and capacitance are both proportional to the size or the via density D,they can be parametrically added into the MNA equation. Let�s first review the well-known thermal-electrical duality. The table shows that the temperature corresponds to the electrical voltage response, and the thermal power corresponds to the input current sources. In addition, there exist the corresponding thermal conductance and capacitance. Animation As a result, the thermal system could be also described by MNA based state equation in both time and frequency domain. In addition, as shown later on, because the via conductance and capacitance are both proportional to the size or the via density D,they can be parametrically added into the MNA equation.

8. 8 Two Distributed Networks for 3D IC All device/dielectric layers and power planes are discretized into tiles A distributed electrical RLC model for power/ground plane A distributed thermal RC model for device/dielectric layer Each via is modeled by a RC pair Moreover, we use two distributed networks to model 3D IC. A distributed electrical RLC model for power/ground plane, and a distributed thermal RC model for device/dielectric layer. In addition, each via is modeled by a RC pair. All device/dielectric layers and power planes are discretized into tiles. Moreover, we use two distributed networks to model 3D IC. A distributed electrical RLC model for power/ground plane, and a distributed thermal RC model for device/dielectric layer. In addition, each via is modeled by a RC pair. All device/dielectric layers and power planes are discretized into tiles.

9. 9 Thermal Model and Analysis Steady-state thermal model and analysis Tiles connected by thermal resistance Heat sources modeled as time-invariant current sources Steady-state temperature can be obtained by directly solving a time-invariant linear equation Let�s further discuss details of thermal model and analysis. In the steady-state thermal analysis, the tiles are connected through thermal resistances. The heat sources are modeled as time-invariant current sources. Then steady-state temperature can be obtained by directly solving a time-invariant linear equation. On the other hand, in the transient thermal analysis, the tiles are connected through thermal resistances and capacitances. The heat sources are modeled as time-variant current sources. Then transient temperature can be obtained by directly solving a time-variant linear equation. Let�s further discuss details of thermal model and analysis. In the steady-state thermal analysis, the tiles are connected through thermal resistances. The heat sources are modeled as time-invariant current sources. Then steady-state temperature can be obtained by directly solving a time-invariant linear equation. On the other hand, in the transient thermal analysis, the tiles are connected through thermal resistances and capacitances. The heat sources are modeled as time-variant current sources. Then transient temperature can be obtained by directly solving a time-variant linear equation.

10. 10 Need of Transient Thermal Modeling Time-variant workload and dynamic power management introduce temporal and spatial thermal power variation Thermal power is the runtime average of cycle-accurate power over thermal time-constant Thermal power decides temperature Why do we need transient thermal analysis? This is because time-variant workload and dynamic power management introduce temporal and spatial thermal power variation, Where thermal power is the runtime average over the thermal time-constant of cycle-accurate power, and it decides the temperature. As a result, the steady-state analysis has to assume a maximum thermal power simultaneously for all regions But it rarely happens and hence can result in an over-design. On the other hand, a transient thermal analysis is accurate but it is also time-consuming. As such, it calls for more accurate yet efficient transient thermal simulation during the design automation Why do we need transient thermal analysis? This is because time-variant workload and dynamic power management introduce temporal and spatial thermal power variation, Where thermal power is the runtime average over the thermal time-constant of cycle-accurate power, and it decides the temperature. As a result, the steady-state analysis has to assume a maximum thermal power simultaneously for all regions But it rarely happens and hence can result in an over-design. On the other hand, a transient thermal analysis is accurate but it is also time-consuming. As such, it calls for more accurate yet efficient transient thermal simulation during the design automation

11. 11 Need of Simultaneous Thermal/Power Co-Design In addition to use a transient analysis, we also propose a Simultaneous Thermal/Power Co-Design. As shown by simulation in this figure, Temperature hotspots usually distribute differently from voltage bounce, Accordingly, a power integrity map tends to result in a biased via stapling pattern in center, And A thermal integrity map tends to result in a uniform via stapling pattern. As a result, Considering thermal and power integrity separately may also lead to over-design. In addition to use a transient analysis, we also propose a Simultaneous Thermal/Power Co-Design. As shown by simulation in this figure, Temperature hotspots usually distribute differently from voltage bounce, Accordingly, a power integrity map tends to result in a biased via stapling pattern in center, And A thermal integrity map tends to result in a uniform via stapling pattern. As a result, Considering thermal and power integrity separately may also lead to over-design.

12. 12 Problem Formulation Therefore, to simultaneously consider the power and thermal integrities with different stapling patterns, We propose a levelized via stamping. As shown by this figure, for a level�0 stapling, the vias are only allocated in the center. And for a level-1 stapling, the plane is first divided into 4 sub planes, and vias are then allocated into 4 centers of sub lanes. Note that Each level has a different via density Di. Correspondingly, we give the problem formulation as follows. Our via planning problem is to find a via density vector D to minimize the total via number. It is constrained by the thermal integrity for each die and power integrity for power plane. In addition, we also consider the constraints of signal congestion and reliability for current density. This problem can be efficiently solved by the sensitivity based method, Where The sensitivity is calculated from the structured and parameterized macromodel.Therefore, to simultaneously consider the power and thermal integrities with different stapling patterns, We propose a levelized via stamping. As shown by this figure, for a level�0 stapling, the vias are only allocated in the center. And for a level-1 stapling, the plane is first divided into 4 sub planes, and vias are then allocated into 4 centers of sub lanes. Note that Each level has a different via density Di. Correspondingly, we give the problem formulation as follows. Our via planning problem is to find a via density vector D to minimize the total via number. It is constrained by the thermal integrity for each die and power integrity for power plane. In addition, we also consider the constraints of signal congestion and reliability for current density. This problem can be efficiently solved by the sensitivity based method, Where The sensitivity is calculated from the structured and parameterized macromodel.

13. 13 Outline Modeling and Problem Formulation Integrity Analysis and Sensitivity based Optimization Experimental Results Conclusions Therefore, next I will talk about the structured and parameterized model reduction to generate macromodelTherefore, next I will talk about the structured and parameterized model reduction to generate macromodel

14. 14 Parameterized System Equation To generate sensitivity, we need first parameterize the system. In this problem, we use two parameters: levelized stapling pattern and the via density for each pattern. The levelized stapling pattern could be described by an adjacent matrix X. For example, if we insert one via in between node 2 and node 6, the corresponding adjacent matrix can be described by X(2,6) as shown in right. In addition, because via conductance and capacitance are both proportional to size or density, one density parameter Di is used for each stapling pattern. As a result, both Di and Xi are parametrically added into the nominal MNA equation below. Note that the state variable here is a total voltage or temperature response. For the purpose of design automation, we need to separate sensitivity from the nominal value. To generate sensitivity, we need first parameterize the system. In this problem, we use two parameters: levelized stapling pattern and the via density for each pattern. The levelized stapling pattern could be described by an adjacent matrix X. For example, if we insert one via in between node 2 and node 6, the corresponding adjacent matrix can be described by X(2,6) as shown in right. In addition, because via conductance and capacitance are both proportional to size or density, one density parameter Di is used for each stapling pattern. As a result, both Di and Xi are parametrically added into the nominal MNA equation below. Note that the state variable here is a total voltage or temperature response. For the purpose of design automation, we need to separate sensitivity from the nominal value.

15. 15 Separation of Nominal and Sensitivity Similar to handle variations in this paper, we first expand the state variable x by Taylor expansion w.r.t. to the via density parameter Di. Then construct an expanded state variables by nominal value and sensitivity w.r.t. Di, Accordingly, the expanded system can be reorganized into a lower block-triangular system according to the expansion order. Figure in right shows the lower-triangular block structure for G_ap. C_ap has a similar structure as well. The system size is enlarged and needs to be reduced. However, previous flat projection can not separate the nominal state variables and their sensitivities. we find that this can be solved by a structure-preserved projection as shown by the following slide. Similar to handle variations in this paper, we first expand the state variable x by Taylor expansion w.r.t. to the via density parameter Di. Then construct an expanded state variables by nominal value and sensitivity w.r.t. Di, Accordingly, the expanded system can be reorganized into a lower block-triangular system according to the expansion order. Figure in right shows the lower-triangular block structure for G_ap. C_ap has a similar structure as well. The system size is enlarged and needs to be reduced. However, previous flat projection can not separate the nominal state variables and their sensitivities. we find that this can be solved by a structure-preserved projection as shown by the following slide.

16. 16 Macromodel by Model Reduction As shown by this figure, constructing macromodel by model order reduction is simply to reduce the system size. One efficient method is to apply Krylov-subspace based projection method. The reduced model can preserve accuracy by matching moments of inputs. However, the existing reduction methods apply a non-structured flat projection. It does not preserve the block matrix structure such as sparsity. In addition, the reduced macromodel does not contains sensitivity information and hence can not be used for design automation efficiently. As shown by this figure, constructing macromodel by model order reduction is simply to reduce the system size. One efficient method is to apply Krylov-subspace based projection method. The reduced model can preserve accuracy by matching moments of inputs. However, the existing reduction methods apply a non-structured flat projection. It does not preserve the block matrix structure such as sparsity. In addition, the reduced macromodel does not contains sensitivity information and hence can not be used for design automation efficiently.

17. 17 Structured Projection (I) Block-diagonally partition the flat projection matrix according to the size of nominal state-variable and sensitivity This can be done as follows. We first Block-diagonally partition a flat projection matrix according to the size of nominal variable and sensitivity. Then we apply the new projection matrix to project the original one, and the reduced system still has a separated nominal values and sensitivities. In addition, because the reduced model preserves the block triangular structure, There is only one LU-factorization of the reduced block in diagonal. This can be done as follows. We first Block-diagonally partition a flat projection matrix according to the size of nominal variable and sensitivity. Then we apply the new projection matrix to project the original one, and the reduced system still has a separated nominal values and sensitivities. In addition, because the reduced model preserves the block triangular structure, There is only one LU-factorization of the reduced block in diagonal.

18. 18 Time-domain Analysis Note that the time-domain transient response could be solved from the reduced system using backward-Euler integration. Because the reduced system preserve the block triangular structure, there is only one LU-factorization of the reduced nominal block in diagonal. Therefore, the nominal response, and sensitivity can be solved separately and efficiently. In addition, the generated sensitivities can be used in any gradient based optimization. We call this method as SP-MACRO. Note that the time-domain transient response could be solved from the reduced system using backward-Euler integration. Because the reduced system preserve the block triangular structure, there is only one LU-factorization of the reduced nominal block in diagonal. Therefore, the nominal response, and sensitivity can be solved separately and efficiently. In addition, the generated sensitivities can be used in any gradient based optimization. We call this method as SP-MACRO.

19. 19 Sensitivity based Optimization With the use of reduced model we can solve the first-order sensitivity as shown below. This procedure provides an efficient calculation of both nominal value and sensitivity. The calculated sensitivity can be further used to update the via density vector D during each iteration. In addition, note that the computation cost of sensitivity could be further reduced when an adjoint Lagrangian method is used for a system with large number of outputs than inputs. With the use of reduced model we can solve the first-order sensitivity as shown below. This procedure provides an efficient calculation of both nominal value and sensitivity. The calculated sensitivity can be further used to update the via density vector D during each iteration. In addition, note that the computation cost of sensitivity could be further reduced when an adjoint Lagrangian method is used for a system with large number of outputs than inputs.

20. 20 Outline Modeling and Problem Formulation Integrity Analysis and Sensitivity based Optimization Experimental Results Conclusions Finally, I will present the experiment results.Finally, I will present the experiment results.

21. 21 Experiment Settings Here is the experiment settings. Read the slide�Here is the experiment settings. Read the slide�

22. 22 Accuracy of Reduced Macromodel I will first show the accuracy of the reduced macromodel. Figure shows transient temperature responses of exact and SP-MACRO models at port 3, 18, and 58 of top layer with step-response input. The responses of macromodels are visually identical to those exact models. I will first show the accuracy of the reduced macromodel. Figure shows transient temperature responses of exact and SP-MACRO models at port 3, 18, and 58 of top layer with step-response input. The responses of macromodels are visually identical to those exact models.

23. 23 Temperature/Voltage Reduction during OPT The next figure shows the temperature reduction at selected location during the procedure of via-allocation by SQP. The procedure stops until that the transient temperature meets the targeted ceiling temperature 52C. The next figure shows the temperature reduction at selected location during the procedure of via-allocation by SQP. The procedure stops until that the transient temperature meets the targeted ceiling temperature 52C.

24. 24 Steady-state vs. Transient

25. 25 Sequential vs. Simultaneous In addition, we further compare the via distribution at different levels. The via pattern for P/G tends to concentrate in low level, but the via pattern for thermal only tends to concentrate in high level. On the other hand, the simultaneous stapling result in a uniform distribution of vias in all levels. In addition, we further compare the via distribution at different levels. The via pattern for P/G tends to concentrate in low level, but the via pattern for thermal only tends to concentrate in high level. On the other hand, the simultaneous stapling result in a uniform distribution of vias in all levels.

26. 26 Conclusions We conclude as follows: Read the slide�We conclude as follows: Read the slide�