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CMOS Adder s Architecture 1

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## CMOS Adder s Architecture 1

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**1. **CMOS Adders Architecture (1)

**2. **2 Contents Half Adder (HA)
Full Adder (FA)
Sign Bit Overflow
Ripple Carry Adder (RCA)
Carry Lookahead Adder (CLA)

**3. **3 Half Adder (1) Half Adder (HA)
Inputs : Pair of single-bits but no a carry-in
Truth Table
Logic functions

**4. **4 Half Adder (2)

**5. **5 Full Adder (1) Full Adder (FA)
Inputs : Two binary numbers and a Carry-in
Truth Table

**6. **6 Full Adder (2) Karnaugh Map

**7. **7 Full Adder (3) Logic circuits of Full Adder

**8. **8 Full Adder (4)

**9. **9 Sign Bit Overflow (1) An erroneous carry into the sign bit of a signed binary number
that results from a sum or difference larger than can be represented by the number of magnitude bits
In unsigned addition, the binary equivalent is
In signed addition, the sum is the same but has a different meaning.
The sum of positive signed binary numbers
Must not exceed 2n-1-1 for numbers having n magnitude bits
Otherwise, there will be an overflow into the sign bit

**10. **10 Sign Bit Overflow (2) Overflow Detection
Requires access to the sign bits of the operands and result
If the sign bits of both operands are the same and
the sign bit of sum is different from the operand sign bits,
?An overflow has occurred

**11. **11 Sign Bit Overflow (3) The Boolean expression for the overflow detector is:

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**22. **22 Carry Lookahead Adder (5) 16-bit Carry Look ahead Adder Block diagram using 4-bit CLA

**23. **23 Carry Lookahead Adder (6) Carry Generation Logic
Where

**24. **24 Carry Lookahead Adder (8) Carry Generation using Group Carry Generate and Propagate Function

**25. **25 Carry Lookahead Adder (7) Carry Generation Logic

**26. **26 Carry Lookahead Adder (8)

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