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Course: High-Speed and Low-Power VLSI  (97.575) Professor: Maitham Shams PowerPoint Presentation
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Course: High-Speed and Low-Power VLSI  (97.575) Professor: Maitham Shams

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Course: High-Speed and Low-Power VLSI  (97.575) Professor: Maitham Shams

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  1. Course: High-Speed and Low-Power VLSI  (97.575) Professor: Maitham Shams Presentation: True Single-Phase Adiabatic Circuitry By Ehssan Hosseinzadeh Special Student

  2. Outline • Introduction • Adiabatic – Switching Circuits • True Single-Phase adiabatic Circuit • Results • Conclusion • References

  3. Introduction • Importance of Reducing Power Dissipation • Techniques =>Parallelism => Pipeline => Transformation => Reduce the Chip wide Supply voltage => Energy Recovery

  4. Conventional Energetic Adiabatic - Switching Circuits • Swinging voltage on capacitor: • - Zero => V • V => Zero • Engergy dissipation per transition • E= ½ CV2

  5. Adiabatic - Switching Circuits • Recovery Energy Ediss= P. T = I2 . R .T = (RC/T) CV2 Adiabatic - Switching Circuits

  6. True Single-Phase adiabatic Circuit • Different Approaches: • Signal voltage swing > Vt of CMOS • => Adiabatic Amplification • Dynamic logic families • => 2N2P, 2N-2N2P, • => True Signle-Phase Energy-Recovery Logic (TSEL) • => Source–Coupled Adiabatic Logic (SCAL)

  7. True Single-Phase adiabatic Circuit • True Single-Phase Energy-Recovery Logic (TSEL) Cascades are composed of alternating PMOS and NMOS gates • TSEL GATES

  8. PMOS • DP: • Vpc: H-L • Vpc  VRP - |vtp| • EP: • Vin: H , Vpc:L • Vpc < VRP - |vtp| • Ddp > |Vtp| • Vpc  VRP - |vtp| • NMOS • EN: • Vpc > VRN + |vtn| • CN: • Vpc  VRN + |vtn|

  9. TSEL Cascades • TSEL Cascades are built by stringing together alternating PMOS and NMOS gates

  10. SCAL Gates • Single Phase power Clock Operation • Tunable Current Source at each Gate

  11. Vbp DP: Vpc: H-L Adiabatlically till Vpc > |Vtp| EP: Vpc: L-H Vbp increase Vdd - |Vbp| > |Vtp| Vpc < Vxp - |Vtp| Dpp > |Vtp| Vpc > Vxp - |Vtp| Vbn Vpc

  12. SCAL Cascades

  13. Results • 8-bit Carry-Lookahead adder (CLAs) Developed in Static CMOS, PAL, 2N2P, TSEL, SCAL (0.5um) Freq: 10 –200 MHz SCAL CLA => 1.5 – 2.5 times more efficient than PAL, 2N2P SCAL CLA => 2 – 5 times less dissipative than purely combinational or pipelined CMOS

  14. Conclusion • True Single-phase adiabatic logic family: • TSEL, SCAL • Source-coupled variant of TSEL => Increase energy efficiency by using tunable current source • Avoid the problems: • Multiple Power-clock schemes - Increased energy dissipation - Layout Complexity in clock distribution, - Clock Skew - Multiple power–clock generator

  15. References • True Single Phase Adiabatic Circuitry, Suhwan Kim and Mario Papaefthymiou • Energy Recovery For Low Power CMOS, WC Athas and N. Tzartanis • Low Power Digital Systems Based on Adiabatic-Switching Principles, William C. Athas