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BUILDING BLOCKS designed at IPHC in TOWER JAZZ CMOS I mage Sensor 0.18 µm process

BUILDING BLOCKS designed at IPHC in TOWER JAZZ CMOS I mage Sensor 0.18 µm process. Isabelle V alin on behalf of IPHC-PICSEL group. INTRODUCTION.

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BUILDING BLOCKS designed at IPHC in TOWER JAZZ CMOS I mage Sensor 0.18 µm process

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  1. BUILDING BLOCKS designed at IPHCin TOWER JAZZ CMOS Image Sensor 0.18 µm process Isabelle Valin on behalf of IPHC-PICSEL group

  2. INTRODUCTION • The building blocks were initially designed in the AMS CMOS 0.35 µm process and have been translated in the TOWER JAZZ CMOS Image Sensor 0.18 µm process including: • Bandgap • Current reference • Bias-DAC • Reference voltage regulator • LVDS • JTAG controller • Those blocks were implemented and tested in several prototype sensors. Isabelle.valin@iphc.cnrs.fr

  3. BANDGAP Vout vs temperature for different process corners Vdd= 1.8 V PSR in process corners, Vdd= 1.8 V • BANDGAP (W. Zhao) • Output voltage: 1.145 V • High power supply rejection < -25 dB • Standard deviation [27 °C] • 9.2 mV Process • 2.5 mV Matching • Temperature coefficient [-45 to 140 °C] < 190 ppm/°C • Supply voltage range: 1.5 to 2 V • Power consumption ~130 µW [Typ, 27°C,1.8 V] • Reset • Dimension : 196.16 x 133.26 µm2 Isabelle.valin@iphc.cnrs.fr

  4. Current Reference (I.Valin) IRef versus Vdd Currentreferenceschematic Iref versus temperature for differentVdd • Reference current: 10 µA • Lowdependency to temperature [-20 to 120 °C] and supply voltage [1.5 to 2 V] • Process variation compensated by • Adjustment of the resistance value with 3 JTAG bits • Power consumption ~415 µW [Typ, 27°C,1.8 V] • Dimension: 94 x 110 µm2 Isabelle.valin@iphc.cnrs.fr

  5. Bias-DAC (G. Bertolone, H. Pham, I.Valin) • 8 bit current mode DAC • Programmable via the JTAG controller • Currentsteeringsegmented architecture: • 2 bit DAC withbinaryweightedcurrentcells • 6 bit DAC with an array of 64 unit currentcells • MonotonicDAC • Range: 0 – 25.5 µA, Step = 100 nA=> Low power consumption • Dimension: 110 x 106 µm2 Isabelle.valin@iphc.cnrs.fr

  6. Reference Voltage Regulator(H.Pham) Architecture of the reference voltage regulator Generation of pixel clamping voltage, discriminatorreference voltages Isabelle.valin@iphc.cnrs.fr

  7. LVDS LVDS receiverschematic 30 cm Test configuration LVDS driver schematic • LVDS receiver and driver (Z. Shi) • 2 layout versions (Basic and Enclosednmos) • LVDS disable option • Standard PAD compatible • LVDS test (K. Jaaskelainen) • Receiver output connected to driver input • Test structure withdifferentialtransmision line (Z = 100 Ω ) of 30 cm length • Test input signal : XILINX IBERT Test Pattern Generator (PRBS-7) • “DC-BALANCED DATA WITH LIMITED RUN-LENGTH“ Isabelle.valin@iphc.cnrs.fr

  8. LVDS Duty Cycle vs Data bit rate Total jitter UI vs Data bit rate Eye amplitude vs Data bit rate • LVDS test results • LVDS receiver + LVDS driver • Maximum data transfert Rate ~ 1 Gbps (or 500 MHz in case of clock signal) • Currentconsumption • 7.6 mA @ static condition • 10.1 mA @ Clock pattern at 1 Gbps Isabelle.valin@iphc.cnrs.fr

  9. JTAG controller (C. Colledani, A. Himmi) • JTAG protocol, IEEE 1149,1 Rev1999 standard • Routed with 2 metal layers Dim. : 735 x112 µm2 Basic hardware elements  Test Access Port (TAP),  TAP Controller,  Instruction Register (IR)  Device ID Register (Inputs: fuse or TIE1,TIE0), readonly mode  Boudary Scan Register  2 specific data registers of 8 bits (read/write mode) • Historyvalidated on MIMOSA Family + Mimosa28/Ultimate (STAR)  TCK Frequency► 40MHz  Boundary Scan Clock Timing analysisresults► slack(setup): 9 ns ► slack(hold): 0.12 ns Test chip ► basic functions OK  TMS Setup/Hold Time ► ~2 ns  Boundary Scan Control Signal  TDI Setup/Hold Time ► ~2 ns  Boundary Scan Serial Data In  S.E.U protection  Standard Flip-Flop replacedwith TMR Memory Cell (Triple ModularRedundancy) Isabelle.valin@iphc.cnrs.fr

  10. SUMMARY • LVDS Driver/Receiver is full characterized. • Other building blocks are validated by several prototype sensors test results but • Those blocks need to be implemented in a test chip for evaluating individually their performances. • To be optimized for power consumption. • To be redesigned without MIM Capacitors when keeping Metal5 & Metal6 for power supply redistribution layers. Isabelle.valin@iphc.cnrs.fr

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